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SERVICE MANUAL 




-128/C128D 
COMPUTER 



NOVEMBER 1987 PN-314001-08 



Commodore Business Machines, Inc. 

1200 Wilson Drive, West Chester, Pennsylvania 19380 U.S.A. 

Commodore makes no expressed or implied war- 
ranties with regard to the information contained 
herein. The information is made available solely on 
an as is basis, and the entire risk as to quality and 
accuracy is with the user. Commodore shall not be 
liable for any consequential or incidental damages 
in connection with the use of the information con- 
tained herein. The listing of any available replace- 
ment part herein does not constitute in any case 
a recommendation, warranty or guaranty as to 
quality or suitability of such replacement part. 
Reproduction or use without expressed permission, 
of editorial or pictorial content, in any matter is 
prohibited. 

This manual contains copyrighted and proprietary information. No part 
of this publication may be reproduced, stored in a retrieval system, or 
transmitted in any form or by any means, electronic, mechanical, 
photocopying, recording or otherwise, without the prior written permis- 
sion of Commodore Electronics Limited. 

Copyright © 1987 by Commodore Electronics Limited. 
All rights reserved. 



CONTENTS 



TITLE 



PAGE 



SPECIFICATIONS 



PARTS LIST 



BLOCK DIAGRAM 
THEORY 



1 
2 
3 



BUS ARCHITECTURE 



8502 MICROPROCESSOR 
Z-80 MICROPROCESSOR 



4 
6 
8 



MEMORY ARCHITECTURE 11 

READ ONLY MEMORY 15 

RANDOM ACCESS MEMORY 17 

MEMORY MANAGEMENT UNIT 20 

PROGRAMMED LOGIC ARRAY 28 

8701 CLOCK GENERATOR 30 

VIDEO INTERFACE 31 

8564 VIDEO INTERFACE CHIP 33 

8563 VIDEO CONTROLLER 36 

8568 CRT CONTROLLER 39 

8580 SID 41 

R/W AMP FDD 47 

I/O - INPUT/OUTPUT CIRCUITS 49 

CASSETTE INTERFACE 49 

KEYBOARD 51 

EXPANSION BUS 52 

SERIAL BUS 54 

TROUBLESHOOTING 

COMMON LINE DEFINITIONS 56 



COMMON I.C.'S (PIN ASSIGNMENTS & LOGIC) 57 



PCB 



PCB ASSEMBLY #310379 REV. 6 

BOARD LAYOUT 63 

PARTS LIST 64 

SCHEMATIC DRAWINGS 66 

PCB ASSEMBLY #310379 REV. 7 

BOARD LAYOUT 70 

PARTS LIST 71 

SCHEMATIC DRAWINGS 73 

RF MODULATOR NTSC 77 

C128 POWER SUPPLIES 78 

C128D MAJOR PARTS 80 

C128D COMPONENT PARTS & BOARD LAYOUT 81 

C128D SCHEMATIC #252451 82 



COMMODORE 128 



GENERAL FEATURES 



64 M 



■ • 



E 



128 MODE 



CP/M MODE 



KEYBOARD 



INPUTS/OUTPUTS 



RECOMMENDED 
PERIPHERALS 



POWER REQUIREMENTS 



PERSONAL COMPUTER 



• Advanced Styling • 100% Compatible with Commodore 64 

• Built-in, Easy to Use DOS support • RAM Expandable up to 51 2K 
RAM Using RAM Disk Option • Upper and Lower Case Character 
Set 

• Built-in BASIC • 3 Separate Modes of Operation 

• 8502 Microprocessor (6502/6510 Compatible) • 6581 Sound 
Interface Chip • 64K RAM • 16K ROM • BASIC 2.0 • 40 x 25 
Lines (320 x 200 resolution) • 16 Colors -\- 8 Sprites 



• 8502 Microprocessor (6502/6510 Compatible) 

• 6581 Sound Interface Chip • 128K RAM (Expandable to 51 2K 
Using RAM Disk Option) • 48K ROM -h 1 6K ROM for DOS 
Support 

• BASIC 7.0 • Machine Language Monitor • 40 x 25 Lines (320 x 
200 resolution) • 80 x 25 Lines (640 x 200 resolution) • 16 
Colors -t- 8 Sprites (40 Column Only) 

• Z80 Microprocessor • CP/M^"*" Plus Version 3.0 

• 128K RAM (Expandable to 512K Using RAM Disk Option) 

• 40 X 25 Lines (320 x 200 resolution) • 80 x 25 Lines 
(640 X 200 resolution) • 1 6 Colors 



• Full Size Typewriter Style • 92 Keys • 14 Key Numeric Keypad 



8 Programmable Function Keys 
40/80 Column Key • No Scroll 



6 Cursor Keys • Help Key 
Line Feed • Escape • Tab 



• Cap Lock • Alt (Not all accessible in 64 Mode) 



• User Port 

• Cassette Port 

• RF/TV Port 

• Audio Input 

• Composite Video 



• Serial Port 

• 2 Game Ports 

• Cartridge Port 

• Audio Output 

• Digital RGBI Video 



• MPS 802, MPS 803, MPS 1000 Printers 

• 1541, 1571 Single Disk Drive 

• 1901 Monochrome Monitor • 1902 Digital RGBI Color Monitor 

• 1 660 and 1 670 Modems • Fully Compatible with Commodore 64 
Software and Accessories in 64 Mode 



1 1 7 Volts AC, 60 Hz, 1 5 Watts 



fSpecifications subject to change without notice 
*CP/M is a registered trademark of Digital Research, Inc. 



1 



PARTS LIST 

C-128 



NOTE: Commodore part numbers are provided for reference orrty mnd 
pBd^ito the avdiaMity of parte from Commodore. Imfustry stamlaKl parte 



* I I 



t * * 



* ' ^ .P^ i i % 



a *: 



^: w : 



Coimectors) shouM be secured locally. Approved cros»4«ferances for TTL <Mtfps, 
eto. we avaNiMe in manual form dwough the Servtee Department. 

parte wH be stocked by Commodore and are indicated on the parte list by 



TOP CASE ASSY 



Top Case 
Keyboard 
Namepiate 
Lamp Holder Set 

LED Assembly 



C 251987-01 

C 310401-01 

C 310400-01 

C 252013-01 

C 250754-01 



BOTTOM CASE ASSY 



Bottom Case 
Foot, Self-Adhesive 
PCB Top Shield 
PCB Bottom Shield 
PCB Insulation Sheet 



C 251988-01 

C 251993-01 

C 252015-01 

C 252016-01 

C 252017-01 



ACCESSORIES 



Users Manuals 
Introductory Guide 
System Guide 

Power Supply 

RF Cable 

Switch Box 

Tutorial Diskette 
CP/M Diskette # 1 
CP/M Diskette #2 



C 319773-01 

C 310638-01 

C 310416-01 

C 326189-01 

C 904778-01 

C 317667-01 

C 317430-01 

C 317431-01 



2 



BLOCK DIAGRAM 



flLPHfl LOC 




CJ 



to 



UJ 
CO 



cc 
in 



cc 

UJ 



< 

AUDIO 



CD 
CC 



Clfl «1 

6526 



Clfi *t2 
6526 



SID 
6581 



B«H COMP 




CD 



CONTROL 



8502 
uPROCESSOR 



80 COLUMN 
VIDEO CHIP 

8563 



CO 

D 

in 

CO 
UJ 



LOGIC 



en 

CD 



16K ROM 



C-64 
BRSIC 

ond 
KERNflL 



VIDEO ROORESS 



VIDEO OflTfl 



16K X 8 

DRAM 



cj 



GQ 




Z-80fl 
uPROCESSOR 



16K ROM 



C-128 

BASIC 

LO 



PLR 



Mode Con tro 1 




m 






CRSENB 



CRS Selects 



MMU 



SHARED flODRESS BUS 



OflTfl BUS 



16K ROM 



C-128 

BASIC 

HI 



16K ROM 



C-128 
KERNAL 

ond 
40/80 COL 
EDITOR 



EXPANSION CARD 



> 



CHIP SELECTS 



CONTROL 





> '/eIe^^ 



GATE 



32K ROM 



C-128 
INTERNAL 
FUNCTION 



CAS 




RflMCASG 



RRMCASl 



The CI 28 System 



DflTfi BUS 



CHARflCTER 

ROM 

2K X 8 





COLOR DfiTfl BUS 



TRANSLATED/SHARED ADDRESS BUS 



LATCH 



MULTIPLEXED ADDRESS BUS 



MUX 



RAS 



128K X 8 DRAM 



CO 

c 

c 

O) 

Ko 



VIC 
856^ 



o 

CJ 

o 



CO 

O 



MODULATOR 



Lu a: 

CO a (x 

C\J z o 

— i UJ CD 

LJ t— >- 

X UJ 



5TNC 

LUM 

CHROMA! 




3 



BUS ARCHITECTURE 




The Processor Bus 



The Processor Bus is the data and address buses that are directly connected to the 8502 processor. 
These buses are designated Dq - D7 for the eight bit data bus and Aq -Ai 5 for the sixteen bit address 
bus. These buses tie the processor to most of the system ROM and I/O devices, including at least 
part of ail System ROM, all built-in Function ROM, the MMU, the PLA, the 8563 Video Processor, 
the SID, and both CIA chips. 

The Processor Bus is in direct communication with the Z-80 co-processor as well. All address lines 
are shared directly by both processors. In order to allow the Z-80 to operate on a 6502 family bus, 
it is necessary to latch data going into the Z-80 and gate the data leaving the Z-80. Thus, the Z-BO 
has a small local data bus, designated ZDq -ZD7. During a write cycle, when AEC is high, Z-80 data 
is gated to the Processor Bus. During a read cycle. Processor Bus data is gated to the Z-80 data bus. 
This read data is transparently latched by the 1 MHz system clock. 

The read and write cycles referred to are, unless otherwise specified, 8502 type bus cycles. The 
Z-80 Read Enable and Write Enable outputs are conditioned using logic to interface with an 8502 
bus cycle, so no distinction is made as to the differences between cycles of the different processors. 

As mentioned above, the Z-80 is not in direct communication with the Processor Data Bus, due 
to the necessity of adapting the Z-80 to 8502 bus protocol. Note, however, that every other device 
and the translated bus (except two that will be explained later) shares the Processor Data Bus as a 
common data bus. 



The Translated Address Bus 



Address 



AEC high. This bus consists of only high order addressing lines, designated TAb - TAi 5. These lines 
reflect the action of the MMU on the normal high order address lines, which may or may not include 
some sort of translation. The MMU can translate the address of page zero or page one in normal opera- 
tion, and it translates the Z-80 address from $0000 thru $0FFF in order to direct it to read the Z-80 
BIOS. A more complete description of MMU translations can be found in the MMU section. Normally 
the Translated Address Bus indirectly drives the DRAMs and the VIC chip by driving the Multiplexed 
Address Buses. It directly drives System ROM 4 address line 12 to allow the Z-80 ROM relocation. 
Finally, this bus becomes address lines 8 thru 1 5 of the C64 compatible expansion port. 

During a VIC cycle or a DMA, the MMU pulls TAi 2 - TAi 5 high, while TAs - TAn are tri-stated. 
This allows the VIC chip to drive TAs - TAi 1 as VIC addresses VAs - VAi 1. 

The Multiplexed Address Bus 

This section actually describes two related address buses, the Multiplexed Address Bus and the 
VIC Multiplexed Address Bus, known respectively as MAq - MA7 and VMAq - VMA7. The VIC 
Multiplexed Address Bus is created during AEC high by multiplexing the high order Translated Ad- 
dress Bus (TAs - TAi 5) with the low order Processor Address Bus (Aq - Ay), controlled via the MUX 
signal. This bus, driven though series resistors, is called the Multiplexed Address bus. The VIC Multi- 
plexed Address Bus is used in addressing the VIC chip registers while the Multiplexed Address Bus 
is the processor's DRAM address for both 64K banks of DRAM. 



4 



BUS ARCHITECTURE (Continued) 



During a VIC cycle, AEC low, the VIC chip address lines must be asserted. There is no completely 
separate address bus for the VIC addresses, so it shares the VMAq - VMA7 and TAs - TAt 1 address 
lines that are otherwise tri-stated during AEC low. Most of the VIC addresses come out of the VIC 
chip already multiplexed, but two of them, VAe and VA7. They do not supply column information, 
as the VIC chip supplies only fourteen bits of addressing. The higher order address bits VA14 and 
VA15 come from CIA 2, as in the C64. Thus, the VIC supplies complete VMAq - VMAy for a VIC 
DRAM access or DRAM refresh. The TAs - TAi 1 supplied by VIC are used in conjunction with another 
addressing bus for non-multiplexed VIC cycle addresses, such as Character ROM and Color RAM 




The Shared Address Bus 



The Shared Address Bus is a non-multiplexed address bus used by both the processor and the VIC 
chip. This is necessary to communicate with common resources, namely the Character ROM and 
Color RAM. During AEC high, the Shared Address Bus, designated SAq - SA7, is driven by Aq - A7, 
the lower order Processor Address bits. The higher order bits needed are supplied by the Translated 
Address Bus, which is also a shared address bus. Thus, the processor is able to access both shared 
items. 



During AEC low, the VIC addresses VAq - VA7 (VMAq - VMAy) must come onto the Shared Ad- 
dress Bus. Since VAq - VAe are actually multiplexed, the row address only must be sent to the Shared 
Address Bus. Thus, the Multiplexed VIC addresses are transparently gated when either RAS or MUX 
are low, but latched when both are high, which would indicate that a column address is about to 
be presented. The high order address bits, as well, are supplied by the shared Translated Address 
Bus. Note that the Shared Address Bus provides the lower eight bits of the expansion port address, 
allowing VIC access to cartridges and some additional drive capability by way of the TTL chips used 
to drive the Shared Address Bus. 



The Color Data Bus 



The Color RAM is written to or read from by a nybble data bus called the Color Data Bus, During 
AEC high, the Color Data Bus is connected to the lower half of the Processor Data Bus via an analog 
switch, allowing the Processor full access to the Color RAM. During AEC low, that switch is opened, 
effectively isolating the Color Data Bus from the Processor Data Bus. In this state, it is driven by the 
VIC extended data bus Ds - Dn. 



The Display Bus 

The Display Bus is a bus local to the 8563 Video Controller VIC chip, consisting of the Display Ad- 
dress, DAo - DA7, and the Bus Display Data Bus, DDq - DD7. This local bus supports the 8563 display 
RAM, which is completely isolated from the rest of the CI 28 system. The Display Address Bus is 
a multiplexed address bus providing addressing to the display DRAM. The Display Data Bus provides 
communication between this DRAM and the 8563. The 8563 also provides row and column strobes 
and dynamic refresh to this DRAM. 



5 



THE 8502 MICROPROCESSOR 




The 8502 is an HMOSII Technology microprocessor similar to the 6510/6502. It is the normal 
operating processor and is used in the C64 and the CI 28 modes. Fully software compatible with the 
6510, hence the 6502, the 8502 also features a zero page port used in memory management and 
cassette implementations. The 8502 is also specified for operation at 2 MHz. The 2 MHz operation 
is made possible by removing the VIC from the system. The VIC chip is never completely removed 
from the CI 28 system, as it continues to function as clock generator and bus arbitrator. However, 
the VIC is removed as a display chip and co-processor, thus the full clock cycle can be devoted to 
processor functioning instead of sharing the cycle with the VIC. The task of video display processor 
is then taken over by the 8563, which can function without the need for bus sharing that the VIC 
required. Since the I/O devices, SID, etc., are rated at 1 MHz only, stretching of the 2 MHz clock 
is used to allow these parts to be directly accessed by the 2 MHz processor, and still keep throughput 
to a maximum. The I/O devices are not affected by the 2 MHz operation as they are still driven by 
a 1 MHz source (and as such, all timer operations remain unchanged), and clock stretching is only 
used to synchronize the 2 MHz machine cycle to the 1 MHz <f>o high time. The clock sources and 
clock stretching capabilities are generated by the VIC chip. 



CLOCK STRETCHING 



When running in 2 MHz mode, the processor clock sometimes must be stretched. This is handled 
by the VIC chip, the processor, and the PLA working together. When an I/O operation is decoded 
during a 2 MHz cycle, the phase relationship between the 2 MHz and the 1 MHz clocks must be con- 
sidered. If the 2 MHz access occurs during 1 MHz ^i , the access to a clocked I/O chip would be out 
of sync hronization with the 1 MHz clock that drives all I/O chips. Thus, during this phase relationship, 
lOACC, from the PLA, signals the VIC chip to extend the 2 MHz clock. Should the 2 MHz cycles take 
place during the 1 MHz 02 cycle, no special attention is necessary. 




Hz 




1 o c 





z 




1 




o 



I 





c c 




X 



X 



X 



PHI 1 



p 



N 




roc 
o c 



> 



T 

p 

1 







y 



y 



n 



c c e s s 



X 



I 



c c 




X 



^ 



V 



D 



X 



HI 




P r o c 
Clock 



N. 



y 



y 




y 



^c c e s 



O 



y 



Clock Stretching in 2 IMHz IMode 



Please take note to consider the speed implications of this. In 2 MHz mode, half of the I/O accesses 
given will occur at an effective speed of 1 MHz. For time critical operations, then, accesses to I/O 
chips are kept at a minimum. 



6 



THE 8502 MICROPROCESSOR (Continued) 



31 5020 
8502 MICROPROCESSOR 



00 (IN) 

RDY 

IRQ 

NMI 

AEC 

VDD 

AO 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

A8 

A9 

A10 

All 

A12 



A13 




1 



2 



00 



RDY 



3 



IRQ 



4 



NMI 



5 



AEC 



6 

7-20 

22,23 



VDD 
A0-A15 



21 
24-30 



VSS 
P0-P6 



31-38 D0-D7 



39 



R/W 



40 



RES 



Phase clock input. This is the dual speed 
system clock for the 128. 
Ready. TTL level input, used to DMA the 
8502. The processor operates normally while 
RDY is high. When RDY makes a transition to 
the tow state, the processor wit) finish the 
operation it is on, and any subsequent opera- 
tion if it is a write cycle. On the next occur- 
rence of read cycle the processor will halt, 
making it possible to tri-state the processor 
to gain complete access to the system bus. 
The Interrupt Request input is a request that 
the processor initiate an interrupt sequence. 
The processor will complete execution of the 

current instruction before recognizing the re- 
quest. At that time, the interrupt mask in the 
Status Code Register wilt be examined, tf the 
interrupt mask is not set, the processor will 
begin an interrupt sequence. The Program 
Counter and the Processor status register will 
be stored on the stack and the interrupt 
disable flag is set so that no other interrupts 
can occur. The processor will then load ttie 
program counter from the memory location 
$FFFE and $FFFF. 

The Non-Maskable Interrupt Request is a 
negative-edge sensitive request that the pro- 
cessor initiate an interrupt sequence. The pro- 
cessor will complete execution of the current 
instruction before recognizing the request. 
The Program Counter and the processor 
status register will be stored on the stack. 
The processor will then load the program 
counter from the memory locations $FFFA 
and $FFFB. 

The Address Enable Control. The Address 
Bus is only valid when the AEC line is high. 
When tow, the address bus is in a high 

impedance state. This allows DMA's for dual 
processor systems. 

5VDC input. 

Address bus outputs. Unidirectional bus 
used to address memory and t/0 devices. The 
address bus can be disabled by controlling 
the AEC input. 
DC ground. 

Bidirectional t/0 port used for transferring 
data to and from the processor directly. The 
Data Register is located at location $0001 
and the Data Direction Register is located at 
location $0000. 

Bi-directional bus for transferring data to and 
from the device and the peripherals. 
The read/write line is a TTL level output from 
the processor to control the direction of data 
transfer between the processor and memory, 
peripherals, etc. This line is high for reading 
memory and low for writing. 
The Reset input is used to reset or start the 
/iprocessor from a power down condition. 
During the time that this line is held low, 
writing to or from the /iprocessor is inhibited. 
When a positive edge is detected on the in- 
put, the /^processor wilt immediately begin 

the reset sequence. After a system initializa- 
tion time of 6 cycles, the mask interrupt flag 
wilt be set and the processor will toad the 
program counter from the contents of the 
memory locations $FFFC and $FFFD. This is 
the start location for program control. After 
Vcc reaches 4.75 volts in a power up 
routine, reset must be held low for at least 2 
cycles. At this time the R/W line will become 
valid. 



7 



THE Z-80 MICROPROCESSOR 




m^^mm 



-^■^ 






■i -- -.■' 






^^- 






* - . 




X ^ 



- -- . \ 



. * 



2i,lM^^:pt 




^ V 










-y 







The Z-80 microprocessor is used as a secondary processor in the CI 28 to run CP/M based pro- 
grams. The Z-80 is interfaced to the 8502 bus and can access all of the devices that the 8502 can 

access. 



Bus Interface 

Since a Z-80 bus cycle is much different than a 65xx family bus cycle, a certain amount of interfac- 
ing is required for a Z-80 to control a 65xx type bus. Since the Z-80 has built-in bus arbitration con- 
trol lines, it is possible to isolate the Z-80 by tri-stating its address line. Thus, the Z-80 and 8502 
both share common address lines. 

The data lines do not interface quite as easily. Due to the shared nature of the bus during Z-80 
mode, it is necessary to isolate the Z-80 from the bus during AEC low. Thus, a tri-stable buffer must 
drive the Processor bus during Z-80 data writes. The reverse problem occurs during a Z-80 read — 
the Z-80 must not read things that are going on during AEC low. It must latch the data that was pre- 
sent during AEC high. Thus, a transparent latch drives the data input to the Z-80. It is gated by the 
Z-80 Read Enable output, and latched when the 1 MHz clock is low. It will be seen that the Z-80 
actually runs during AEC low, but that the data bus interfaces with it only during AEC high. 

Control Interface 

The Z-80 control interfacing must provide useful clock pulses to the Z-80 and must tailor the Z-80 
Read and Write Enable signals for the 8502 type bus protocol. The Z-80 clock is provided by the VIC 
chip, and is basically a 4 MHz clock that only occurs during <Ao low, as seen in the Z-80 bus timing 
diagram. This insures that the Z-80 is only clocked when it is actively on the bus. One additional pro- 
blem that arises in clocking the Z-80 is that while all of the 8502 levels, and most of the Z-80 levels, 
are TTL compatible, the Z-80 clock input expects levels very close to five volts. For that reason, the 
ouptut from the VIC chip is processed by a transistor switching circuit to give a full amplitude clock. 
This circuit uses the nine volt supply, thus, the nine volt circuit must be operational for the Z-80 to 
function. 

System _ 
Clock 



Z-8G 
C 1 ock 

Z-8Q 
flddr 

Z-8Q 

Data 

Me n o r y 
Data 

Latch 
Data 




Address Vo 1 i d 





Data VqI Id 





\ 



Valid 





Val Id 



Z-80 Bus Timing 



8 



THE Z-80 MICROPROCESSOR (Continued) 



The Z-80 is designed to have explicit Read, Write and I/O cycles, where an I/O cycle is distinct 
from a memory cycle. The 65xx family uses only memory mapped I/O and thus, for a 65xx bus, all 
I/O devices appear as memory locations, and all non-write cycles appear as read cycles. The Z-80 
communicates cycle information via two control lines, the Read Enable and Write Enable lines. The 
0128 uses the Read Enable line of the Z-80 to gate the Processor Bus data to the Z-80 data bus. 
The Write Enable interfacing is somewhat more complicated. 

The Write Enable Circuitry consists of a rising-edge triggered D-Type flip-flop and an SR flip-flop. 
The D-flop is triggered by the rising-edge of the 1 MHz clock. The positive output of the SR drives 
the D-input, and the Q output gated with AEC drives an open coll ector inverter,_which in turn drives 
the R/W line of the 8502 bus. The"? input is driven by the Z-80 WE, and the R input is driven by 
the Q out put of the D-flop. Normally the D-input is low, resulting in an 8502 read cycle. When the 
Z-80 WE signal falls, it sets the SR flop, causing the D-input to rise. This line remains high, even if 
the Z-80 WE should rise again. When the 1 MHz clock rises, this high level is clocked, causing an 
8502 write _cycle that will last one complete 1 MHz c ycle. When the Write signal is passed by the 
D-flop, the Q output will reset the SR flop. If no more WE signals come, the D-flop will once again 
set 8502 Read mode. 



Processor Switching 

It is important in normal operation for the Z-80 and 8502 to operate as co-processors, communicating 
between each other. This is, however, only serial co-processing, not to be considered parallel co- 
processing or multiprocessing. Only one processor may have the bus at any one time. This is impor- 
tant in several ways. First, the 01 28 system must power up with the Z-80 as the master processor. 
This is because the Z-80 will not power up cleanly, and may accidently access the bus when power- 
ing up. Thus, it is made master on powerup and can do anything it likes to the bus. Also, the Z-80 
can start up certain 064 applications that would cause the 8502 to crash, thus again it is the logical 
choice for startup processor. After some initializations, the Z-80 will start up the 8502 in either 01 28 
or 064 mode, depending upon if a cartridge is present. 

The second reason for processor switching is to allow the Z-80 to access 8502 Kernel routines. 
For standardized programs, or for any I/O operation not supported in the Z-80 BIOS, the Z-80 can 
pass on the task of I/O to the 8502. Since the Z-80 sees BIOS ROM where the 8502 sees its pages 
through F, the Z-80 can operate without fear of disrupting any 8502 pointers or the stack in RAM 
Bank 0. 



The Z-80 can receive a bus grant request from the MMU, via Z80EN, or from the VI C chip, via BA. 
Since the VIO control line is used for DMAs, that is not of immediate concern. Th e Z80E N action, 
however, is, since it is the mec hanism by which processors swap control. When the Z80EN line goes 
high, it triggers a Z-80 BUSRQ. The Z-80 will relinquish the bus by pulling BUSACK low. This action 
drives the 8502 AEO high and, providing VIC does not request a DMA, w ill also drive the 8 502 RDY 
line high, enabling the 8502. To switch back, a low on the Z-80 BUSRQ will result in Z-80 BUSACK 
going high, tri-stating and halting the 8502. 



9 



THE Z-80 MICROPROCESSOR (Continued) 



9061 50 
Z-80 MICROPROCESSOR 



All 

A12 

A13 

A14 

A15 

PHI 

D4 

D3 

D5 

D6 

VCC 




HALT 
ME MREQ 

lORG 



1 




40 


2 




39 


3 




38 


4 




37 


5 




36 


6 




35 


7 




34 


8 




33 


9 




32 


10 


Z-80 


31 


11 


H Pro- 


30 


12 


cessor 


29 


13 




28 


14 




27 


15 




26 


16 




25 


17 




24 


18 




23 


19 




22 


20 




21 



A10 

A9 

A8 

A7 

A6 

A5 

A4 

A3 

A2 

A1 

AO 

VSS 

RFSH 



18 



HALT 



19 



MEMREQ 



20 



tORQ 




21 



RD 




WAIT 
BUSAK 




RD 



1-5. 
30-40 



A0-A15 



6 

7-10, 
12-15 

11 
16 



PHI 
D0-D7 



VCC 
INT 



17 



NMt 



1 6 Bit tri-stating Address Bus. Used for 
1 6 bit memory address during memory 
cycles, used for 8 bit I/O address during I/O 
cycles. This allows up to 256 input or 256 
output ports. During refresh time, the lower 7 

bits contain a valid refresh address. 
Single phase system clock. 
Input/Output Data Bus, capable of tri-stating, 
used for 8-bit data exchanges with memory 
and t/0 devices. 
5VDC input. 

Interrupt Request. Active (ow input, driven by 
external devices. If the in terrupt flag IFF is 
enabled, and the BUSRQ line is not active, 
the processor will honor the requested inter- 
rupt at the end of the current instruction. 
When the Z-80 acknowledges an interrupt, it 
gerTera tes an interrupt acknowledge signal 
(loRQ during M^) at the beginning of the 
next instruction cycle. There are three 
different modes of response to a given 
interrupt. 

Non-Maskable Interrupt. Active low input. 
This interrupt is edge triggered and cannot be 
masked against. It is always recognized at 
the end of the current instruction, forcing the 
Z-80 to take a restart at location $0066. The 
program counter is automatically saved Jn the 
stack to allow a return from the interrupted 
program. Not e tha t continuous WAIT cycles 
can delay an NMI by preve nting th e end of 
the current cycle, and that BUSRQ will over- 
ride NMI. 



22 



WR 



23 



BUSAK 



24 



WAIT 



25 



BUSRQ 



26 



RESET 



27 



Mi 



28 



RFSH 



29 



VSS 



Halt State. Active low output indicating that 
the Z-80 has executed a HALT instruction 
and is awaiting some kind of interru pt befo re 
execution can continue. While in the HALT 
state, the CPU continuously executes NOPs 
to continue refresh activity. 
Memory Request. Active low, tri-state output 
that indicates that the address bus holds a 
valid address for a memory read or write 
operation. 

Input/Outpu t Requ est. Active low, tri-state 
output. The lORQ signal indicates that the 
lower half of the address bus holds a valid 
addre ss for an I/O read or write operation. An 
lORQ signal is also generated with an Mi 
signal when an interrupt is being acknowl- 
edged to indicate that an interrupt response 
vector can be placed on the data bus. An 
interrupt can be acknowledged during M-); 
I/O operations never occur during Mt- 
Memory Read. Active low, tri-state output. 
RU indicates that the CPU wants to read data 
from memory or from an I/O device. This 
signal is generally used to gate read data 
onto the data bus. 

Mem ory Write. Active low, tri-state output. 
WR indicates that the data bus holds valid 
data to be processed by memory or by an I/O 
device. 

Bus Acknowledge. Active low output, used 
to indicate to any device taking over the bus 
that the Z-80 has gone into tri-state and the 
bus has been granted. While in this mode it 
cannot refresh dynamic memory. 
Wait. Active tow input, used to drive the 
Z-80 into wait states. As long as this signal 
is low, the Z-80 will execute wait states, 
allowing this signal to be used to access 
slow memor y and I/O devices. While the 
Z-80 is in a WAIT state, it cannot refresh 
dynamic memory. 

Bus Request. Active low input that is used to 
request the CPU address, data, tri-statable 
output control signals to all go tri-state for 
bus sharing and DMAs. The lines go tri-state 
upon termination of the current machine 
cycle. 

Reset. Active low input which forces the pro- 
gram counter to zero and initializes the Z-80, 
which will set interrupt mode 0, disable inter- 
rupts, and set registers I and R to zero. 
During RESET, address and data buses tri- 
state and all other signals go inactive. 
Machine Cycle One. Output, active low. This 
signal indicates that the current machine 
cycle is the OP code fetch of an instruction 
execution . Du ring execution of a two byte 
op-code, Ml is generated as each b yte is 
fetched. M^ also occurs with lORQ to in- 
dicate an interrupt acknowledge cycle. 
Refresh. Active low output used to indicate 
that the address bus holds a refresh address 
in its lo wer seven bits. Thus, the current 
MREQ signal should be used to do a refresh 
read to all dynamic memories not refreshed 
from an alternate source. Ay is set to zero 
and the upper eight bits contain the I register 
at this time. 
Ground. 



10 



MEMORY ARCHITECTURE 



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s. 








Ex terno 1 
ROMs 



C-64 
Mode 



C-128 
Mode 



$FFFF 
$FCGG 



$FGGO 



$EQOQ 



$DQQ0 



$8GQ0 _ 



$6GQ0 



$4060 



$2000 



$1GGG 
$0400 
$0002 




KERNflL 



U8 Colunn Edtter- 



a 



/ 



^ 



I/O and CHRROH 



KERNRL 



N.L. Nonltof 



1/0 «r>d CHRROK 



40/ee Colunn Editor 



$CGO0 



$flOO0 



Longuoge 
Cord 



a 



Ex tens 1 on 
Cord 




^ 



/ 



Bnsic HI 



V«r«lon 3*A 



< 



BASIC LG 



V«rslon a. 



RRM Bonk 




RRM Bonks 
1 - 3 



_BK C9ft ^n Boundru 



V 



K Cow^j^ Boun dru 



W .CoFOTpn ^un dru 



LGK Connon Boundry 



r 



r 



Internal ^_/ 



Fund I on ROM 

CFROMl. FROHZl 

Function ROM EHlarnol. 
(HIROH, LORONI 



/ 



r 



64 K 
RAM 

(DflStC T«xtl 



j6K Cofwpn Bouridru 



_fiK Cowwon Bou n dru ^ 



IK Conwon Bo i^pd rij, , i^ 

Hsaa wfl Pon~r 




64 K 
RAM 

(VorlQblss) 



'' 



/ 



/ 



7K 



\ 



\ 



\ 



HI 

; SPACE 



/ 



/ 



/ 



/ 



\ 



\ 



\ 



\ 



/ 



A 




M=I': 



or 



rr 



HOT/ 



. MID 
) SPACE 



/ 



/ 



/ 



/ 



\ 



\ 



\ 



LO 
■ /SPACE 



/ 



/ 



/ 



/ 



/ 



/ 



I 



$0GO0 I 



CI 28 Memory Map 



CI 28 ROM Mamory Organization 

The memory map is an important consideration in maintaining C64 compatibility. The standard map 
is shown for the C64 mode. The CI 28 basically becomes a C64 when in C64 mode. 



11 



MEMORY ARCHITECTURE (Continued) 



CI 28 mode is achieved at system reset, and is controlled by a bit in the MMU configuration register 
(See MMU Circuit Theory, page 20). In CI 28 mode, the MMU asserts itself in the CI 28 memory map 
at $FFOO and in the I/O space starting at $D500. Use of MMU registers, located at $FFOO, allows 
memory management without actually having the I/O block banked in at the time and with a minimum 
loss of contiguous RAM. The MMU is removed from the memory map in C64 mode but is still used 
by hardware to manage memory. 

The ROMs in C64 mode, both internally and externally, look just like C64 ROMs. The internal BASIC 
and KERNAL provide the C64 mode with the normal C64 operating system in ROM. This ROM actual- 
ly duplicates some of the ROM used in CI 28 mode, but is necessary, as it is not accessible from 
CI 28 mode. In CI 28 mode, up to 48K of Operating System is present, with the exact amount being 
set by software control. This allows quicker access to underlying RAM by turning off unneeded sec- 
tions of the Operating System. 

The External ROMs represented on the memory map are those used in the C 64 mode , an d obey 
the C64 rules for mapping, i.e., cartridges assert themselves in hardware via the EXROM and GAME 
lines. External ROMs in CI 28 mode are mapped as banked ROMs, such that when the system is in- 
itialized, all ROM slots are polled for the existence of a ROM and the ROM's priority if one exists. 
This allows much more flexibility than the hardwire ROM substitution method, since the Kernel and 
Basic ROMs can be swapped out for an application program, swapped out for external program con- 
trol, or turned off all together. This banking manipulation is accomplished by writing to the Configura- 
tion Register at location $0500 or $FFOO, in the MMU. 

The hardware also features the ability to store preset values for the configuration and force a load 
of the Configuration Register by writing to one of the LCR (Load Configuration Register) registers. 



CI 28 RAM Memory Organization 

Refer again to the 0128 Memory Map. The RAM present in the system is actually composed of 
two 64K by 8 bytes of contiguous DRAM. The RAM is accessed by selecting one of the two banks 
of 64K according to the RAM banking rules set in the RAM Configuration Register of the MMU. The 
area shown as RAM is representative of what the /iProcessor would see if all ROM were disabled. 
Bank switching can be accomplished in one of two ways. 

The bank in use is a function of the value stored in the Configuration Register. A store to this register 
will always take effect immediately. An indirect store to this register, using preprogrammed bank con- 
figuration values, can be accomplished by writing to one of the indirect load registers, known as LCRs 
(Load Configuration Register), located in the $FFOO region of memory. By writing to an LCR the con- 
tents of its corresponding PCR (PreConfiguration Register) will be latched into the configuration register. 
Refer to the MMU section on page 20 and the Alternate Memory Configurations on the following page. 

When dealing with 64K banks of memory at once, it may be desirable to bank in bank 1 but still 
retain the system RAM (Stack, Zeropage, Screen, etc.). The MMU has provisions for what is referred 
to as common RAM. This is the RAM that does not bank, and is programmable in size and as to whether 
it appears at the top, bottom, or both in the memory map. The size is set by bits and 1 in the RAM 
Configuration Register (RCR). If the value of the bits is zero, 1 K will be common. Values of one, two, 
and three produce common areas of 4K, 8K, and 1 6K respectively. If bit 2 of the RCR is set, bottom 
memory is held common, if bit 3 is set, then top memory is common. In all cases, common RAM 
is physically located in bank 0. 



12 



MEMORY ARCHITECTURE (Continued) 





/^ 


7\ 


1 
] 

1 

SEGQEL 


BK KERNflL ROM 


/ 
/ 

/ 

/ 
/ 
) 


SDOQFI . 


4K I/O 


JCQGfl _ 


yK RAM tBUFFERl 


$0000 


8K BASIC ROM 

] 


$8Q0Q 


8K RAM 


^w ^^^ ^^r ^^r ^^r-^^H ^^^^^ 

$40QQ 


i 
1 

j 
1 

16K RRM 


$0ooeL 


16K RAM 

i 


^T VV ^HV VV %V^^^ ^^^^H 








Y 


$EOQQ 


8K KERNRL ROM 

1 


/ 

/ 

/ 
/ 


$O0OFI . 


4K I/O 


1 
1 

SCQGfl ^ 


4K BflM 


1 
1 

1 

$8QGQ_ _ 


16K RfiM 

1 
1 

1 


$4000 ; 


IBK RAM 


$0009 


16K RRM 



LORAM 
HIRAM 
GAME 
EXROM 



1 
1 
1 
I 



This Mop Is the 
Default Henory Map 



LORRM 
HIRAM 
GAME 
EXROM 




1 
I 
X 



This Mop Used For 
Softload Longuagas 





/ 


7 


$E0QG_ 


8K RAM 


/ 
/ 
/ 

1 

1 
1 

/ 
/ 

1 

1 

1 

/ 


JDQGG- - 


4K 1/0 


■ ^^r ^^F ^^F ^^^^^B^^H ^^ 

*C8Qn 


UK RAM 


$8090. _ 


16K RAM 


jyQDQ. 


16K BAM 


1 

JGQQG- 


16K RAM 


^^ ^v vr ^v v^^^^ ^^^^m 






/ 




$E0GQ 1 


8« KERNflL ROM 


/ 
/ 
/ 

/ 

1 
1 

/ 

1 

/ 
/ 


1 

$DQQa_ ^ 


MK 1/0 


^^" ^^ ^^ ^^^^^^^^ ^^ 

SCOQR . 


4K RAM (BUFFER) 


1 
1 

$neQQ_ 


8K ROM 
(CARTRIDGE) 


*80Qa. _ 


8K RAH 


^ ^hr vr vr v^^BB ^^BH 
1 

SUBQGL 1 


15K RRM 


$0090 , 


16K RAM 



LORRM 

HIRAM 

GAME 
EXROM 


^ 


1 


1 
X 


or 






LORHM 
HIRRM 

GAME 
EXROM 


» 


I 

G 






Thl 6 Mop Used For 
6QK of RAM and 
1/0. Note that the 
second setup renowes 
the character ROM. 



LORflM 
HIRRM 
GAME 
EXROM 



Q 
I 

G 
G 



This Hep Used For 
8K ROM Plug-Ins that 

do not raqulre BASIC 





/ 


y 


$CQGn 


16K RAM 


/ 
/ 


1 

1 
1 

] 

SBGQGL 


!6K RAH 


i 
$4G0Q_ 


16K RflM 


i 

$0000 


16K RAH 


^ ^^ ^^ ^^ ^^^^^r ^^^^m 




H^^^^^^ 




/ 


7 


SEOGG 


1 

8K KERNflL ROM 


/ 
/ 
/ 

/ 
/ 


1 

$DGDf) I 


ilK 1/0 


1 
1 

*CGGa_ „ 


4K RRM (BUFFER) 


] 

$8000 


16K ROM 
ICRRTRIDGEl 

1 

i 


^n ^^ ^^^ ^^^ ^^^^^^ ^^^^^ 

$4000 


15K RAM 

1 


1 

$G00G_ 


15K RRM 



LORRM 


= 





HIRflM 


— 


G 


GOME 


= 


1 


EXROM 


^ 


X 


or 






LORRM 


= 





HIRRM 


= 





GAME 


^ 


X 


EXROM 


— 


Q 



This Mop Used For 
Full 64K RAM Access 



LORflM 
HIRRM 
GOME 
EXROM 



1 
1 





This Mop Used For 
16K Plug-in ROMs 
thol do not roqulr 

BASIC 



C64 Alternate Memory Configurations 

Zero page and page one can be located (or relocated) independently of the RCR. When the pro- 
cessor accesses an address that falls within zeropage or page one, the MMU adds to the high order 
/iProcessor address, the contents of the PO register pair or the PI register pair, respectively, and puts 
this new address on the bus, including the extended addressing bit Aie. RAM banking will occur as 
appropriate to access the new address. Writes to the PO and PI registers will be stored in a prelatch, 
until a write to the respective Pxl register occurs. This prevents a PxH register from affecting the 
translated address until both high and low bytes have been written. 

At the same time, the contents of the PO and PI registers are applied to a digital comparator, and 
a reverse substitution occurs if the address from the 8502 falls within the page pointed to by the 
register. This results in not just relocating the zero or one page but swapping the zero or one page 
with the memory that it replaced. Swapping only occurs if the swapped area is defined as RAM, i.e., 
System or Function ROM must always be at their assigned addresses and thus should not be back- 
substituted. Note that upon system reset, the pointers are set to true zero and true one page. 

For VIC chip access, one bit in the MMU status register is substituted for extended address line 
A16, selecting the proper CAS enable to make it possible to steer the VIC to anywhere in the 128K 
range. Note that AEC is the mechanism that the MMU uses to steer a VIC space address, i.e., when 
AEC is low a VIC access is assumed. This results in the VIC bank being selected as well for an outside 
DMA, since this too will pull the AEC line low. 



13 



MEMORY ARCHITECTURE (Continued) 



MMU and I/O Memory Organization 

The block of memory represented by the I/O Block is an expanded view of the memory block entitled 
I/O + CHAROM, as shown in the CI 28 memory map. When the I/O block exists, access to VIC, SID, 
and I/O, as well as the addition of the MMU can be accomplished. All I/O functions remain as they 
were previously on the C64 with the exception that the MMU and the 80 Column chip have been 
added. With the exception of four registers that are asserted in the zero page in CI 28 mode, all new 
MMU registers appear in an unused slot in the I/O Memory block, though they will only appear in 
CI 28 mode. Detailed descriptions of the MMU registers can be found in the MMU section on page 20. 



$DFFF 

$DFGG 



$DEGG 

$DOGG 

$DCGG 



$D8GG 

$D7GG 

$DSGG 

$D5GG 

$04GG 



1/02 



I/Gl 



CIfltt2 



cin«i 



COLGR RAM 



[RESERVED) 



8563 



$DGGG 



MMU 



SID 



VIC 



/ 



I/O Block 



14 



READ ONLY MEMORY 




In C64 mode, the operating system resides in 1 6K of ROM, which includes approximately 8K for 
Kernal and 8K for Basic. In CI 28 mode, the operating system resides in 48K of ROM and includes 
advanced Kernal and Basic features. The Kernal, by definition, is the general operating system of 

the computer, with fixed entry points into usable subroutines. The entry table for the Kernal is located 
in memory at addresses $FF40 - $FFF9, exiuding of course the MMU registers at $FFOO - $FF04. 
There is also a CHARACTER ROM, 8K x 8, which resides on the Shared Bus, shared by the VIC chip 
and the processor. The C64 OS ROM is wired so as to appear as two chunks of non-contiguous 
ROM, copying the actual C64 ROM memory map. Provision is included to handle system ROM as 
either four 16K x 8 ROMs or as two 32K x 8 ROMs. All internal CI 28 function ROMs will be the 
32K X 8 variety. 



Rom Banking 

Refer to the MMU Register Map on page 20. Note that the Configuration Register (CR) controls 

the type of ROM or RAM seen in a given address location. Dependent on the contents of the CR, 

ROM may be enabled and disabled to attain the most useful configuration for the application at hand. 

ROM is enabled in three memory areas in CI 28 mode, each consisting of 1 6K of address space. The 

lower ROM may be defined as RAM or System ROM, the upper two ROMs may be System ROM, 

Function ROM, Cartridge ROM, or RAM. In C64 mode the C64 memory mapping rules apply, which 

are primitive compared to those used in CI 28 mode. C64 ROM is banked as two 8K sections, BASIC 

and KERNAL, according to the page zero port and the cartridge in place at the time. No free banking 
can take place when a cartridge is in place. 



In the CI 28, if an address falls into the range of an enabled ROM, the MMU will communicate the 
status of ROM to the PLA decoder via the Memory Status lines. Essentially, the MMU looks up in 
the Configuration Register which ROM or RAM is set. The various combinations possible are shown 
on the 01 28 Memory Map found on page 1 1 . The banking scheme, the way it is implemented, allows 
up to 32K of internal, bankable ROM for use such as Function Key Applications programs, and will 
support 32K of external bankable ROM. Various combinations of ROM are possible, and can be noted 
by studying the configurations for the Configuration Register. 



8K X 8 



A7 

A6 

A5 

A4 

A3 
A2 

A1 
AO 
DO 
D1 
D2 

vss 



1 




24 


2 




23 


3 




22 


4 




21 


5 




20 


6 


2364 


19 


7 


ROM 


18 


8 




17 


9 




16 


10 




15 


11 




14 


12 




13 



vcc 

A8 
A9 
A12 

CSi 

A10 

All 

D7 

D6 

D5 

D4 

D3 



1-8, 

18,19, 

21-23 

12 

9-11, 

13-17 

20 

24 



A0-A12 



Vss 

D0-D7 



CSi 

Vcc 



Address Bus Inputs. 

Ground. 

Data Outputs. 

Chip Select. 
5VDC Input. 



15 



READ ONLY MEMORY (Continued) 



NC 
A12 
A7 
A6 
A5 
A4 
A3 
A2 
A1 
A0 
DO 
D1 
D2 
GND 



NC 
A12 
A7 
A6 
A5 
A4 

A3 

A2 

A1 

A0 

DO 

D1 

D2 

GND 



PIN 
CONFIGURATION 



1 




28 


2 




27 


3 




26 


4 




25 


5 




24 


6 


23128 


23 


7 


ROM 


22 


8 




21 


9 




20 


10 




19 


11 




18 


12 




17 


13 




16 


14 




15 



16Kx8 ROM 



PIN 
CONFIGURATION 



1 




28 


2 




27 


3 




26 


4 




25 


5 




24 


6 




23 


7 


23256 


22 


8 


ROM 


21 


9 




20 


10 




19 


11 




18 


12 




17 


13 




16 


14 




15 



vcc 

CS3 

A13 
A8 
A9 
All 

A^O 

CS2 

D7 

D6 

D5 

D4 

D3 



VCC 
A14 

A13 

A8 

A9 
All 

CS'i.CE 

A10 

CS"2 

D7 
D6 
D5 
D4 
D3 



1 


NC 


Not Connected. 


2-10, 






21, 


A0-A13 


Address Bus Inp 


23-26 






11-13, 
15-19 


D0-D7 


Data Outputs. 


14 


GND 


Ground. 


20 


CS2 


Chip Select, 


22 


CSv CE 


Output Enable. 


27 


CS3 


Program Enable. 


28 


VCC 


5VDC Input. 



1 


NC 


Not Connected. 


2-10, 






21, 


AO- A 1 4 


Address Bus ln| 


23-27 






11-13, 
15-19 


D0-D7 


Data Outputs. 


14 


GND 


Ground. 


20 


CS2 


Chip Select. 


22 


CSi, CE 


Output Enable. 


28 


VCC 


5VDC Input. 



32K X 8 ROM 



16 



RANDOM ACCESS MEMORY 




The CI 28 System contains 1 28K of processor-addressable 41 64 DRAMs in the 64K x 1 configura- 
tion, organized into two individual 64K banks. Additionally, the system contains 1 6K of video display 
4416 DRAMs (16K x 4) local to the 8563 CRT Controller, and 8K of STATIC RAM used as VIC 
COLOR RAM. 

RAM banking, described in detail in the MMU section, is controlled by several MMU registers: the 
Configuration Register, the RAM Configuration Register, and the Page Zero and Page One Pointers. 
Simply put, the Configuration register controls which 64K bank of RAM is selected, the RAM Con- 
figuration Register controls if and how much RAM is kept in common between banks, and the Pointer 
registers redirect the zero and one pages to any page in memory, overriding the effect of the two 
configuration registers. In the system, RAM bank select is achieved via gated CAS control. 



2016 
2K X 8 STATIC RAM 



A? 

A6 

A5 

A4 

A3 

A2 
Al 

AO 

l/Oo 
l/Oi 

1/02 

vss 




1 


24 


2 


23 


3 


22 


4 


21 


5 


20 


6 


19 


7 


18 


8 


17 


9 


16 


10 


15 


11 


14 


12 


13 



vcc 

A8 
A9_ 

WE 

OE 

AlO 
CS 

1/07 
1/06 
I/O5 

I/O4 
I/O3 



1-8, 
19, 22 

23 

9-11, 

13-17 
12 

18 
20 
21 
24 



*ioO- 



A«a 



*3 



AoO 



6ec> 




Aq-a 1 



Acidress Bus Inputs. 



I/O0-I/O7 Common Data Input/Output Lines 



Vss 

CS 
OE 
WE 

Vcc 



Ground. 

Chip Select Enable, Low Active. 
Output Enable, Low Active. 
Write (Input) Enable, Low Active 
5VDC Input. 




MEMORV MATRIX 
128 X 16 X 8 



O Vcc 



O V 



CEB 



BUFFER 



I/O GATE « COL DEC 



t 



CE8 




BUFFER 



r^ 



CEB 




«Oo 



I/Or 



Functional Diagram 



17 



RANDOM ACCESS MEMORY (Continued) 



4164 
64K X 1 DYNAMIC RAM 



NC- 


1 


16 


DIN- 


2 


15 


WE- 


3 


14 


RAS- 


4 


13 


A0- 


5 


12 


A2- 


6 


11 


A1- 


7 


10 


VCC- 


8 


9 



vss 

CAS 

DOUT 

A6 

A3 
A4 

A5 
A7 



1 


NC 


Unused. 


2 


DIN 


Data Input. 


3 


WE 


Write Enable. Low active control input. 


4 


RAS 


Row Address Strobe Input. Low active. 


5-7, 
9-13 


A0-A7 


Address Bus Inputs. 


8 


VCC 


5VDC Input. 


14 


DOUT 


Data Output. 


15 


CAS 


Column Address Strobe Input. Low active. 


16 


VSS 


Ground. 



WE 



R/W CLOCK 
GENERATOR 




RAS 



RAS CLOCK 
GENERATOR 



CAS 



CAS CLOCK 
GENERATOR 




UJ 
(0 
(0 



A7 
( A6o 



< 

X 

(0 

UJ 





M 




UJ 



IL 

3 



AO 




(0 

(0 

UJ 



1 



0) 

S 

< 

z 

0) 





UJ 




(A 




< 




R/W SWITCH 



MEMORY 
ARRAY 



ROW DEC. 




C= 3 C =^ ROW DEC 



MEMORY 
ARRAY 



MEMORY 
ARRAY 



ROW DEC. 



(0 



0) 

3 




O 




MEMORY 
ARRAY 



a 



o 



o 
a 



a 



o 



o 
a 



a 



o 



o 



UJ 

o 



MEMORY 
ARRAY 



UJ 

3 



MEMORY 
ARRAY 




O 



MEMORY 
ARRAY 




ROW DEC 



O 

u 




L 



0) 

a. 
< 

z 

0) 



UJ 



0) 




UJ 
0) 



DATA IN 
BUFFER 




DIN 



DATA OUT 
BUFFER 



DOUT 



VCC 



VSS 



VBB GENERATOR 



MEMORY 
ARRAY 



Functional Diagram 



18 



RAN 



»It 



M ACCESS MEMORY (Continued) 



4416 
16K X 4 DYNAMIC RAM 





1 


18 


ENABLE- 


D0- 


2 


17 


D1- 


3 


16 


WE- 


4 


15 


RAS- 


5 


14 


A6- 


6 


13 


A5- 


7 


12 


A4- 


8 


11 


VDD- 


9 


10 



vss 

D3 

CA§ 

D2 

A0 

A1 

A2 

A3 

A7 



1 


ENABLE 


2,3, 
15,17 


D0-D3 


4 


WE 


5 


RAS 


6-8, 
10-14 


A0-A7 


9 


VDD 


16 


CAS 


18 


VSS 



Output Enable (€*). 

Common Data Input/Output Lines. 

Write (Input) Enable. Low Active. 
Refresh Address. Low Active. 

Address Bus Inputs. 

5VDC Input. 

Column Address Strobe. Low Active 

Ground. 




CLOCK GEN 
NO. 1 




COLUMN 
DECODER 




SENSE AMPS 
I/O GATING 



DATA 



BUFF 




STORAGE CELL 
ARRAY 




DO4 



Functional Diagram 



19 



THE MEMORY MANAGEMENT UNIT 



FOLD OUT SCHEMATIC SHEET 2, PAGE 74, FOR EASY REFERENCE. 



^ 



The MMU is designed to allow complex control of the CI 28 system memory resources. It handles 
all of the standard C64 modes of operation in a fashion as to be completely compatible with the C64. 
Additionally, it controls the management of particular CI 28 modes including the Z-80 mode. 



Summary of MMU functions: 

• Generation of Translated Address Bus, TAg 



TA 



15 



• Generation of control signals for different processor modes — CI 28, C64, Z-80 



• Generation of CAS select lines for RAM banking. 

• Generation of ROMBANK (MSq^ MS-|) lines for ROM banking. 

The MMU is the mechanism by which the various memory modes shown in the CI 28 Memory Map 
are chosen. Additionally, the MMU provides for Z-80 mode, which was not shown on that diagram. 
Following is a description of the MMU register types. Note that in C64 mode the MMU completely 
disappears from the system's memory map. Note that the data out of the MMU is valid only on AEC 

high. This is necessary to avoid bus contention during a VIC cycle. 



$FFQ4 

$FFQ3 

$FFG2 

$FFG1 

$FFGG 



$D5GB 

$D5Gn 

$D5G9 

$D5G8 

$D5G7 



$D506 

$D5G5 

$D5QU 

$D5G3 

$D5Q2 

$D5G1 



$D5GG 



/ 


/ 


LCRD 


LCRC 


LCRB 


LCRR 


CR 


-/- 






/ 

/ 
/ 

/ 


/ 

/ 

/ 

_/ 

/ 

/ 

-/- 

-/- 

/ 
/ 

-/- 


VR 


r^ ^ 


PIL 


p n h 


POL 
RCR 

1 


MCR 


PCRD 


PCRC 


PCRB 


PCRR 


CR 


-/' 



- LORD CGNFIGURRTION REG D 

- LORD CGNFIGURRTION REG C 

- LORD CGNFIGURRTION REG 

- LORD CONFIGURRTION REG fl 



_Z_ CGNFIGURRTION REGISTER 



-VERSION REGISTER 
4-PRGE I POINTER HIGH 
-PRGE 1 POINTER LOW 
-PRGE G POINTER HIGH 
-PRGE POINTER LOW 
-RRM CONFIGURRTION REGISTER 
-MODE CONFIGURRTION REGISTER 
-PRECONFIGURRTION REGISTER D 
-PRECONFIGURRTION REGISTER C 
-PRECONFIGURRTION REGISTER B 
-PRECONFIGURRTION REGISTER R 
L/ _CGNFIGURRTION REGISTER 



MMU Register Map 



20 



THE MEMORY MANAGEMENT UNIT (Continued) 



CR=$D50Q=$FFQQ 



PCRn=$D5Ql 
PCRB=$D502 
PCRC=$D5Q3 
PCRD = $D50Ll 



(LCRR=$FF01) 
(LCRB=$FFQ2) 
(LCRC=$FF03) 
(LCRD=$FF04) 




= 

I/O Spoce 1 = 
ROM LO Space 



fll6 



System I/O 
HI ROM Spoce 

G = Susten ROM 
1 = RRM 



ROM MID Spoce 



ROM HI Spoce 



GQ 
01 

10 
1 1 



tRflM BfiNK Q-1) 



EXPRNSION 



Configuration Register 
Preconfiguration Register 



Systen ROM 

INT. FUNC. ROM 
EXT. FUNC. ROM 
RAM 



The Configuration Register 

The Configuration Register, CR, controls the ROM, RAM, and I/O configuration of the 01 28 system. 
It is located at $0500 in I/O space and at $FFOO in system space. Some of the bits in this register 
are at times reflected by hardware lines MSq and MSi in 0128 mode, depending upon how RAM 
and ROM have been set. These MS lines are used to inform the PLA about the type of memory in 
a particular address range. In 064 mode, MSq and MSi are always high, and the selection of RAM 
and ROM is done by the PLA using standard 064 banking methods. The MS lines are alternately refer- 
red to as ROMBANK lines. They will be referred to as MS lines in this section in the interest of simplicity. 

In 0128 mode, bit controls whether an I/O space, $0000 — $DFFF, or a ROM/RAM access oc- 
curs. A low will select I/O, a high will enable some kind of ROM/RAM access, the nature of which 
is controlled by other bits in this register. The value of this bit is stored in a prelatch, until the fall 
of the clock, in order to prevent its changing in an unstable situation. Note that when not I/O space, 
the ROM/RAM access is controlled by the defined ROM Hi configuration bits, which are described 
later. This bit resets to 0. When the I/O bit is low, MMU registers $0500 to $D50B will assert 
themselves. When the bit is high, these registers disappear from the memory map. MMU registers 
$FF00 to $FF04 are always available in 0128 mode. The hardware line l/OSE always reflects the 
polarity of this bit when in 01 28 mode. In 064 mode the l/OSE line, the hardware line driven by this 
bit, is completely ignored by the PLA, and the MMU is never asserted, even when 064 I/O is enabled. 
The 064 method of selecting I/O via HIROM and CHAREN takes over here. The I/O hardware line 
remains in its set state when in 0128 mode, even though it has no effect in this mode. 

Bit number 1 controls processor access to ROM low space, $4000 — $7FFF, in 0128 mode. If 
the bit is high, the area will appear as RAM, and a RAM access, CAS enable, will be generated to 
the appropriate RAM bank, which is determined by other bits in this register. If low, system ROM 
will be located in the space. This bit affects the memory status lines MSq and MSi which are decod- 
ed by the PLA to generate ROM chip selects. Selecting ROM here will drive both memory status lines 
low when the processor address falls within the specified low space range. This bit resets low to 
include the 0128 Basic Low ROM. Of course in 064 mode, this bit is ignored. 

The next two bits, bits 2 and 3, determine for 01 28 mode the type of memory that will be located 
in the mid space, $8000 — $BFFF. If they are both low, system ROM will be located here. If bit 2 
alone is high, internal function ROM is located here. External function ROM appears for bit 3 being 
alone high, and RAM appears, along with the proper CAS generation, for both bits set high. These 
bits also affect the hardware memory access lines. When in the aforementioned mid block address 
range, MSq will reflect the status of bit 3, and MSi will reflect the status of bit 2. These bits both 
reset low to start out with Basic Hi. C64 mode ignores these bits. 



21 



THE MEMORY MANAGEMENT UNIT (Continued) 



Bits 4 and 5 determine the contents of the Hi block, $C000 — $FFFF, for CI 28 mode, and have 
no effect on C64 mode. As with the mid space, both bits zero will set up system ROM, bit 4 high 
will set up internal function ROM, bit 5 high will set up external function ROM, and both bits high 
will set up RAM. Note that the I/O configuration bit, when set for I/O space, will leave the area from 
$D000 to $DFFF as I/O space, regardless of the values of these bits. If not set for I/O space, $0000 
to $DFFF will contain the character ROM if the ROM chosen is System ROM. As with the other ROM 
selection bits, these bits are reflected by the memory status lines when this region of address is ac- 
cessed. Bit 5 corresponds to MSq and bit 4 to MSi . Both of these bits reset to low to permit Kernal 
and Character ROM to power up in this address space. Note that there is always a hole in high ROM 
during CI 28 mode for the MMU registers at $FFOO to $FF04. This hole is brought about by holding 
both MS lines high and both CAS enable lines high. These bits are ignored in C64 mode. 

Finally, bit 6 controls the RAM bank selection. When low, it will select bank by drop- 
ping CASq. When high, it will select bank 1 by dropping CASi. Bit 7 is unassigned at the present, 
left for future expansion. Note that a RAM share status that is non-zero will override the normal CAS 
enable generation to provide CASq for all shared memory. Also, note that when the proper CAS enable 
is generated, any area of memory, even if that area does not have its ROM bank bits set for RAM, 
is accessed. It is up to the PLA to block CAS for a read from ROM. This allows RAM bleed through 
on a write to ROM. For any access to the MMU registers from $FF00 to $FF04, in any CI 28 mode 
configuration, both CAS enable lines and both MS lines will be high. Note that in C64 mode, the bank 
used follows the same rules as in CI 28 mode, though of course banks cannot be changed once in 
C64 mode. 



The Preconfiguration Mechanism 

The Preconfiguration Mechanism is a feature of the MMU that allows the Configuration Register 
to be loaded with one of several memory configurations, with a minimum of time and memory on 
the part of the user. The scheme makes use of two sets of registers, the Preconfiguration Registers 
and the Load Configuration Registers. 

The Preconfiguration Registers (PCRA — PCRD) are used to store several different memory con- 
figurations that may be accessed with a single store instruction. The format of each preconfiguration 
register is the same as for the Configuration Register but, when a value is stored to a preconfigura- 
tion register, no immediate effect takes place. They occupy I/O space from $D501 to $D504. These 
registers always reset to all zeros. 

Load Configuration Registers (LCRA — LORD) directly correspond with the preconfiguration registers 
on a one-to-one basis. A write to a Load Configuration Register causes the contents of the correspond- 
ing Preconfiguration Register to be transferred to the Configuration Register. A read of any Load Con- 
figuration Register returns the value of its corresponding Preconfiguration Register. Load Configura- 
tion Registers are located in system space from $FF01 to $FF04. Neither the Load Configuration 
Registers nor the Preconfiguration Registers have any effect in C64 mode. These registers reset to 
all zeros. Note that these, and the configuration register at $FFOO, will always be available, completely 
independent of the ROM, RAM, or bank configuration defined for Hi ROM space. Any address in this 
range will cause the MMU to force both memory status lines and both CAS enable lines high. 



22 



THE MEMORY MANAGEMENT UNIT (Continued) 



MCR=$D5Q5 




Pro 



Mode 




1 



z-ee 

850D 



EXPANSION 

Q = Input 
FSDIR 1 = Output 

/GRME Sense 
/EXROM Sense 

nc M J ^ = C128 

OS Mode 1 = C64 

40/80 Sense 



Mode Configuration Register 

The Mode Configuration Register 

The control of the current system mode is governed by the Mode Configuration Register, MCR. 
It controls which processor, 8502 or Z-80, and which operating system mode, C64 or CI 28, is cur- 
rently in operation, and handles other overhead of the different operating modes. This register is located 
in the I/O space at $D505. 



Several of the bits in this register function as bidirectional ports, including the FSDIR, GAME, EX- 
ROM, and 40/80 bits. This type of port functions like an output port. If a value is written to the port, 
its hardware line will reflect that value written, and a read will return that value. The only exception 
to this is if an external source is pulling down the corresponding port line. When pulled down, a read 
of the port will return a low. Once the external source has been removed, a read will return the value 
previously stored. Thus, as an input, the port can be driven low, but not high, by an external source. 
Under each bit description, both the input and output functions of each port bit will be described 
in detail. 

The first bit, bit 0, controls which processor is enabled. It is reflected by the output line Z80EN. 
When low, it indicates that the processor is the Z-80. This is the reset configuration, and will cause 
the Z-80 processor to be active and all accesses to memory to follow the Z-80 mapping rules. In Z-80 
mode, any address to RAM bank in the range from $0000 to $OFFF will be translated to the cor- 
responding address in the range from $0000 to $DFFF, where the Z-80 CP/M BIOS physically exists 
in System ROM. Additionally, the memory status lines MSq and MSi , will reflect system ROM (both 
low) for accesses in the range of the BIOS, and the page zero and page one offset pointers will be 
disabled. RAM can still be banked by the OR Ai 6 bit, which controls CASq and CASi . When in bank 
one, the BIOS ROM disappears, allowing the RAM from $0000 to $FFFF to be used by the system, 
and enabling the page zero and one offset pointers. 

A change to this processor select bit is held in prelatch until a clock transition, in order to prevent 
processor changing in the midst of an instruction execution. Bringing this bit high will cause the Z-80 
to be disabled and the 8502 to take over. Upon system power up, the Z-80 will turn itself off and 
bring up CI 28 mode by setting this bit and allowing the 8502 to take over. 

Bits 1 and 2 are unused, but are reserved for future expansion as possible port lines. Currently, 
they will return high if read, and cannot be written to. 

Bit 3 is the FSDIR control bit. It is used as an output to control the fast serial disk data direction 
buffer hardware, and as an input to sense a fast disk enable signal. This bit is a bidirectional port 
bit as explained above, and its hardware line is called FSDIR. 



23 



THE MEMORY MANAGEMENT UNIT (Continued) 



Bits 4 and 5 are the GAME and EXROM sense bits, respectively, which are implemented as bidirec- 
tional p orts as expl ained above. As inputs, they directly reflect the ha rdware cartr idge co ntrol lines 
GAME and EXROM as used in C64 mode, CI 28 cartridges do not use EXROM and GAME, so if they 
are detected in 01 28 mode, a 064 cartridge is present and 064 mode should be asserted. They have 
no dedicated 0128 function. 



The operating system mode is set by bit 6. This bit is cleared to zero upon reset and its presence 
enables all MMU registers and other 01 28 features, as well as asserting the 01 28 control line in hard- 
ware. Setting this bit removes the MMU from the memory map and sets the system up in 064 mode. 
Note that the 0128 MS3 hardware line reflects a logical inversion of the level of this bit. 

Bit 7 is used to detect the status of the screen mode switch, as presented in hardware to the Sense40 
column pin. If this bit is high, the 40/80 column switch is open, if low, the switch is closed. The display 
mode will be set according to a software interpretation of this bit. This bit is a bidirectional port bit, 
but its output function is undedicated at this time. 



RCR=$D506 




Shore Rnount 



Shore S to tus 



01 
10 
11 

00 
Ql 
10 

11 



IK 
UK 
8K 
16K 

No Shore 
Shore Bo t ton 
Shore Top 
Shore Both 



EXPANSION 



VfllS (VIC RAM BfiNK 0-1) 

EXPRNSION 



RAM Configuration Register 



Ttie RAIVi Configuration Register 

The RAM Configuration Register sets up the RAM segmenting parameters for both the processor 
and the block pointer for the VIC chip. This register is located in the I/O space at $D506. 

Bits and 1 function together to determine the size of the RAM to be shared between banks, assuming 
that sharing is enabled. With common RAM, the RAM bank bits of the configuration register are basically 
overridden, as the selected bank of RAM will be used for the non-common areas, while bank will 
be used for the specified common areas. ROM and I/O block configuration bits, however, are still 
important. If the value of the bits together is 0, then IK of RAM is held common. If the value is 1, 
then 4K; 2, then 8K; 3, then 16K. These bits have no effect in C64 mode, and the reset value of 
both bits is defined to be zero. 



Bits 2 and 3 function to determine how and if RAM is kept common. If both are low, no sharing 
takes place. If bit 2 is set, the bottom RAM is shared. If bit 3 is set, the top RAM is shared. Both 
may be set at the same time for sharing both top and bottom memory. The reset configuration sets 
both of these bits zero, such that no common memory is present. 

The next two bits, numbers 4 and 5, are not used in this MMU. They are available for possible future 
expansion. They read low, and cannot be written to. 



24 



THE MEMORY MANAGEMENT UNIT (Continued) 



Bit 6 functions as a RAM bank pointer for VIC. It is used to drive CASq low when set low or CASi 
low when set high, thus selecting either RAM bank or RAM bank 1 for the VIC, independently from 
the processor bank. When in 2 MHz mode the 80-column chip takes over, causing the VIC to be disabled. 
This disabling is affected by the VIC chip itself holding AEC constantly high, and thus is not directly 
effected by actions of the MMU. Note that since a VIC cycle is detected by AEC low, that any DMA 
will put the MMU into VIC configuration, as it too brings AEC low. This allows independent bank selec- 
tion for DMAs in 80 column mode. 



Bit 7 is currently unused. 



PQH-$D5Q8 

PlH=$D50fl 



PxH 



///////// 


765432 1 Q/ 




fll6 



EXPANSION 



PQL-$D507 
P1L=$D5Q9 



PxL 




Page Pointer 



The Page Pointers 



fl8 
fl9 

fllG 
fill 
fll2 
fll3 

fll5 



The page pointers are four registers that allow independent relocation of pages zero and one, when 
running under either processor. These are especially useful when running under the 8502 as they 
help to remove some of the zero page and stack size limitations normally associated with 6502 family 
processors. 

For zero page relocation, the MMU provides the Page Zero Pointer High (POh) and Page Zero Pointer 

Low (POl) registers. Bit of the POh register corresponds to translated addresses TAi g for any zero 
page access, $0000 — $OOFF, controlling the generation of CASq or CASi depending on whether 
it is low or high. The remaining bits are currently unused, and will always return zero. These bits over- 
ride the RAM bank bits, the ROM block, and the I/O block bits to determine which physical page 
appears as zero page for all zero page accesses. A write to the POh register is stored in prelatch until 
a write to the POl register occurs. Bits to 7 of the POl correspond to Translated Addresses TAs 
to TAi 5 for any zero page access, thus relocating the zero page. Any access to the area that has 
become the relocated zero page will be switched back to the original zero page if that area is mapped 
as RAM. If mapped as ROM, then the reverse mapping is not done, allowing access to the ROM. A 
write to this register sets up the zero page transfer, which can occur as soon as the next low clock 
cycle. Register POl is located in the I/O space at $D507, while register POh is located at $D508. 



25 



THE MEMORY MANAGEMENT UNIT (Continued) 



The registers for page one relocation, the Page One Pointer High (P1h) and the Page One Pointer 
Low (PIl) do for page one essentially what POh and POl do for the zero page. The functions and 
bit correspondences are exactly the same. PI l is located in the I/O space at $D509 and Pl h at $D50A. 
Note that both register pairs are initialized upon reset to reflect true page zero and true page one ac- 
cess for the 8502 processor. Note that these registers continue to take effect in Z-80 mode, as well 
as in 8502 mode, when set to bank one. When set to bank zero, they are disabled to provide true 
Z-80 BIOS access. 



VR=$D50B 




MMU Vers i on 

Bonk Version 



Version Register 



System Version Register 



The final register is the System Version Register, which is located at $D50B in the I/O block. This 
register is a read-only register that returns a code containing the version of the MMU and the size 
and capability of the system's memory. The lower nybble, bits through 3, contain the version of 
the MMU in the system. The upper nybble, bits 4 through 7, contains a code relating the number 
of memory blocks available in the system. This allows software to compensate for any later systems 
with more available memory, and should make it quite simple for the current CI 28 to remain com- 
patible with any software written in the future for an expanded C256, etc. system. The initial CI 28 
will read a 2 here, indicating two 64K blocks are available. A zero in this nybble would indicate six- 
teen 64K blocks. 



26 



THE MEMORY MANAGEMENT UNIT (Continued) 



310389 
8722 MEMORY MANAGEMENT UNIT 



1 

2 
3-10 



VOD 
RESET 

TA8-TA15 



VDD 

Reset 

TA15 

TA14 

TA13 
TA12 

TA11 

TA10 

TA9 

TA8 





I/O 




MSI 

MSO 

AEC 

MUX 

AO 

A1 

A2 

A3 

A4/5 

A6/7 

A8 




SENSE40 



1 28/64 
EXROM 



GAME 



FSDIR 

zSUen 

D7 

D6 

D5 

D4 

D3 

D2 

D1 

DO 

VSS 

PHip 

R/W 

A15 

A14 

A13 

A12 

All 
A10 
A9 



11,12 



CASo, 
CASi 



13 



I/O SEL, 
MS2 



14,15 MSq. MSi 



16 



AEC 



17 



MUX 



18-31 A0-A15 



32 



R/W 



33 



PHIo 



34 
35-42 

43 



VSS 
D0-D7 

Z80EN 



44 



FSDIR 



45 



GAME 



46 



EXROM 



47 



48 



128/64, 
MS3 

40/80 



5VDC input. 

System Reset. This input initializes internal 

registers on a power up or hardware reset. 

Translated Address outputs. Tri-stated for 

VIC cycles during AEC, provides translated 

physical address for use on the Multiplexed 

Address Bus and the Shared Static Bus. 

TAi2 ^o TAi5 are each defined to have an 

internal, depletion mode pullup with an 

equivalent resistance of 3.3Kn. TAg to TA-| -j 

each go tristate during VIC time (AEC low). 
Column Address Strobe. The CAS output 

lines control DRAM banking. CASq enables 

the first bank of 64K, CASi enables the 

second bank of 64K. 

I/O Select, Memory Status 2. This output is 

identified by both identifiers. It is used to 

select memory mapped I/O in C128 mode 

and is also know as MS2. In C128 mode, 

this line always reflects the polarity of the I/O 

bit. It is ignored by the PLA in C64 mode, 

and remains high throughout 064 mode. 

Memory Status 0, 1 . Also called ROMBANKq 

and ROMBANK1, these outputs control ROM 

banking for all ROM slots. These lines are 

used to decode ROM bank selection for any 

ROM access in CI 28 mode. If they are both 

low, a system ROM has been selected. If 

MSi is high alone, then a built in function 

ROM has been selected. If MSq is alone high, 

then an external function ROM has been 

selected. Finally, if both are high, the RAM 

that occupies the particular slot has been 

selected. In C64 mode the PLA completely 

ignores these tines. 

The Address Enable Control indicates 
whether the 8502 processor or the VIC has 
access to the shared bus. When low, VIC or 
an external DMA has the bus and VA'^g and 
VA17 have the processor bus, and no pointer 
or BIOS translation takes place. 
The Memory Multiplex signal, used to clock 
various sections of the MMU. 
AO - A3, A8 - A1 5: Addresses from the 
microprocessor. Used to derive chip selects 
as well as multiplexed address lines. 
A4/5, A6/7: Combined addresses from the 
microprocessor. Used along with simple 
addresses, combined in this fashion to lower 
the pin count of the MMU. 
R/W: System Read/Write control line. This in- 
put is high for a processor read, low for a 
processor write. 

Presystem clock. Used for early transition of 
gated signals on write operations. Processor 
address is valid on the rising edge and data is 
valid on the falling edge. 
System Ground. 

Data inputs from the microprocessor. Used 
for writing to internal registers. 
This output is used to enable the Z80 pro- 
cessor and disable the normal operation of 
the 8502 processor. It goes low to indicate 
Z-80 mode, high for all other modes. 
Fast Serial Direction. This port is a bidirec- 
tional line that in output mode controls the 
data direction of the fast serial disk interface. 
Game ROM Enable. This signal is used to 
sense the GAME line on the expansion con- 
nector in C64 mode and as the color RAM 
bank control line in CI 28 mode. 
External ROM Enable. This signal is used to 
sense the EXROM line on the expansion con- 
nector in C64 mode and as an expansion 
control line in CI 28 mode. 
This output directs the system to act in 
either CI 28 or C64 mode. It goes low to in- 
dicate C64 mode, high for CI 28 mode. 
Sense 40/80. This bidirectional port is 
used in input mode to sense the 40/80 
column switch. It detects whether or not the 
switch is closed. The output mode is not 
used at this time. 



27 



THE PROGRAMMED LOGIC ARRAY 



.. -.^ 



FOLD OUT SCHEMATIC SHi£T 2. PAGE 74, FOR EASY REFERENCE 



fj f 



liM^ 



The 8721 CI 28 PLA is a programmed version of the Commodore 48 Pin Programmable Logic 
Array. It provides all of the chip selects and other decoded signals that were necessary for the C64, 
along with a number of such signals new in the CI 28 system. 

Summary of PLA functions: 



Control all ROM selects (KERNAL, 
BASIC, FUNCTION, EXTERNAL) in a 
operating modes. 



• VIC chip select. 

• Color RAM chip select. 

• Character RAM chip select. 



• Gated write enable to color RAM. 



Latched write enable to DRAMs. 



Z-80, I/O decoding, for Z-80 I/O cycle 
and Z-80 memory mapping. 



Data bus direction signal. 

I/O group chip select (includes 1/0-1, 
1/0-2, CIA-1, CIA-2, SID, 8563). 



I/O access signal indicating an I/O 
operation is occuring. 



• Column Address Strobe Enable for 
DRAM. 



• Z-80 select decoding. 



Chip Select Generation 

The PLA device is responsible for defining the banking rules for ROM and RAM that the system 
will follow. The chip generates chip selects for all ROM and the VIC chip. It generates an enable for 
any other I/O device in the map, and can enable or disable CAS based upon what else is enabled. 
In CI 28 mode, decisions are made using the processor addresses and the four mode status lines: 
ROMBANKLO, ROMBANKHI, I/O SELECT, and CI 28/64. The CI 28 mode banking scheme is quite 
straightforward and simple. In Z-80 mode, the selection mechanism becomes even simpler, thanks 
to the I/O cycle of the Z-80 processor. 

C64 chip selects account for the bulk of the PLA font. The C64 selects I/O, RAM, and ROM based 
upon the internal control lines BA, HIRAM, LORAM, and CHAREN. The status of these lines, and the 
decoded addresses, determine for any given time which, if any, chip is sele cted. When a cartridge 
is inserted, two additional control lines come into play — EXROM and GAME. Various combinations 
of these lines cause different memory maps to be asserted, all based upon the PLA font. 



Other PU^ Functions 

The PLA performs a variety of functions other than chip selects. It creates the write enable strobes 
for both DRAM and Color RAM. In CI 28 mode, the C64 control lines HIRAM, LORAM, and CHAREN 
are not needed, since the MMU controls the more sophisticated CI 28 method of banking. Thus, these 
lines are used to extend the functionality of the CI 28 at little or no additional cost in hardware. The 
CHAREN line is used in CI 28 mode to turn the Character ROM on and off in VIC address space. In 
the C64, the presence of this ROM was a function of the VIC bank selected. In CI 28 mode, the ROM 
can appear or disappear in any VIC bank. 

The second of the new functions uses LORAM and HIRAM to select one of two Color RAM banks. 
The level of LORAM selects the bank that will be seen during processor time, the level of HIRAM 
selects the bank that will be seen during VIC time. Thus, a program can swap between two full color 
pictures very clearly, or the processor can modify one full color picture while displaying another. 



28 



PROGRAMMED LOGIC ARRAY (Continued) 



315012-01 
PROGRAMMABLE LOGIC ARRAY 



A15 

A14 

A13 

A12 

All 

A10 

VICFIX 

DMAACK 

AEC 

R/W 

GAME 

EXROM 

Z80 EN 

Z80 I/O 

64/128 

I/O SE 

ROMBANKHI 

ROMBANKLO 

VMA4 

VMA5 
BA 

LORAM 

HIRAM 

VSS 



1 


48 


2 


47 


3 


46 


4 


45 


5 


44 


6 


43 


7 


42 


8 


41 


9 


40 


10 


39 


11 


38 


12 8721 37 


1 3 PLA 36 


14 


35 


15 


34 


16 


33 


17 


32 


18 


31 


19 


30 


20 


29 


21 


28 


22 


27 


23 


26 


24 


25 



vcc 

CLK 




CHAROM 
COLRAM 
GWE 
I/O ACC 
VIC 

CASENB 
OWE 
DIR 
I/O CS 
M 1 

ROM 1 

ROM 3 
ROM 4 

frSm 

CLRBNK 
ROM H 
ftOM L 
SI5EFJ 
N/C 

128/256 
VA14 
CHAREN 



1-6 

7 
8 

9 

10 

11 

12 
13 



27 



28 
29 



32 

33 
34-37 

38 



39 



40 



41 



42 
43 

44 

45 
46 
47 
48 



A10-A15 

VICFIX 

DMAACK 

AEC 

RAW 
GAME 

EXROM 

Z80EN 



14 


Z80 I/O 


15 


64/128 


16 


I/O SE 


17,18 


ROMBANKLO 




ROMBANKHI 


19,20 


VMA4,VMA5 


21 


BA 


22, 


LORAM 


23, 


HIRAM 


25 


CHAREN 


24 


VSS 


26 


VA14 



128/256 



N/C 
SDEN 



30,31 ROM L, ROM H 



CLRBNK 
FROM 
ROM 1-4 

I/O CAS 



DIR 



DWE 



CASENB 



VIC 

I/O ACC 

GWE 

COLRAM 
CHAROM 

CLK 

VCC 



Address input from 8502 microprocessor. 
Input to modify CASENB latching for VIC timing. 
DMA Acknowledge input pulled high in CI 28 
system. 

Address Enable Control input from VIC. 
Read/Write input from 8502 microprocessor. 
Input from the expansion port indicating an exter- 
nal ROM in C64 mode. Unused in CI 28 mode. 
Input from the expansion port indicating an exter- 
nal ROM in C64 mode. Unused in CI 28 mode. 
Input from the Z80 BUSACK line indicating the 
Z-80 relinquishes the bus. 
Z80 input requesting I/O. 
High input sets CI 28 mode. 
I/O select input from MMU. 
Input from MMU to indicate ROM bank 
status. 

Input from VIC multiplexed address. 
Bus Available Input from VIC. 
Memory configuration signals input from the 
8502 port. They are used for C64 mode memory 
mapping and CI 28 mode extensions. 
Ground 

VIC address 14 input from the 6526. Selects video 
map in C64 mode. 

Input line to indicate whether 1 28K or 256K ROMs 
are installed in the system. High for 1 28K, low for 
256K. 

No connection. 

SD enable output used to enable the buffer be- 
tween the data bus and the S DATA bus. 
Active low outputs. They are the chip selects for 
expansion ROMs. 
Output for color RAM bank select. 

Function ROM chip select output. Active low. 
ROM chip selects for operating system ROM. Ac- 
tive low output. 

Active low output used as I/O chip select. Enables 
external decoder for CIA1 and 2, I/O 1 and SID 
and 8563. 

Data Bus Direction control output for the Data to 

S Data buffer. 

Active low output for DRAM write enable. MUX 

latches the output in the PLA. 

RAM Column Address Strobe Enable. Used to gate 

CAS outputs from MMU. The active low output 

is latched by MUX in the PLA. 

Active low output to select the VIC chip. 

Indicates access to a 1 MHz part, typically an I/O 

part. Used by the VIC to stretch the 2 MHz clock. 

Active low output used as write enable for color 

RAM. 

Color RAM chip select, valid for MPU and VIC. 

Character ROM chip select, valid for MPU and VIC. 

Common clock input from VIC. 

5VDC input. 



29 



8701 CLOCK GENERATOR 





PIN 
ASSIGNMENT 




CRYSTAL 
OSCILLATOR 



N/C- 


1 


16 


vss- 


2 


15 


N/C- 


3 


14 


N/C- 


4 


13 


RESET- 


5 


12 


DOT- 


6 


11 


PAL - 


7 


10 


COLOR- 


8 


9 



N/C 

Vdd 

XTL IN 
XTL OUT 

Vdd 

N/C 
N/C 

vss 



COLOR 

FREQUENCY 

OUTPUT 

BUFFER 




o1 



o2 



OUTPUTS 



FREQUENCY DOUBLER 

AND 

INTERNAL CLOCK 

GENERATOR 



ol 



o2 



FREQUENCY 
DIVIDER 



PAL =4.5 
NTSC = 3.5 



H 




#0 
PULSE 



ff3 
PULSE 



ol 



o2 



Pin 6 
Pin 8 



Dot Clock 
Color Clock 



8.1818 MHz. 
14.31818 MHz 



PULSE 
SHAPER 



DOT 

FREQUENCY 

OUTPUT 

BUFFER 




Block Diagram 



The oscillator circuit uses an external crystal to generate a precise frequency, compatible with either 
PAL or NTSC video systems. This frequency can be fine-adjusted using an external trimmer capacitor. 
The output of this oscillator is buffered and becomes the color clock output. It also goes to the fre- 
quency doubler circuit. From there, a pair of non-overlapping clocks are generated (PHI1 and PHI2). 

These go to the frequency divider which in turn generate a pair of signals, #0 pulse and #3 pulse. 
Their frequency is determined by the state of the PAL/NTSC input pin. These two pulses go through 
some digital delays, and with the help of PHI1 and PHI2 are re-combined to form the dot clock fre- 
quency. This signal is then buffered and sent out via the dot clock pin. 



XTL OUT 




01 

02 




"LJTJlJ"LJlJTJlJ\rLJl-^^ 



#0 PULSE 

#3 PULSE 

<t> COLOR 









(t> DOT 




NTSC Clock Timing Diagram 



30 



THE VIDEO INTERFACE 



FOLD OUT SCHEMATIC SHEET 3, PAGE 75, FOR EASY REFERENCE 



The CI 28 VIC video interface hardware allows the connection of a standard commercial television 
and/or a color monitor. The monitor may accept either a composite video signal or separate chroma 
and luminance/sync signals in addition to an audio signal. This output is very similar to the ouptut 
of the 8 pin video C64 units. 

The CI 28 also provides 80 column video interfacing. The available 80 column display is RGBI and 
monochrome, able to interface to most RGBI TYPE I monitors and most 80 column compatible 
monochrome monitors. 



The VIC Video Interface 



The VIC video interface supplies a 40 column display in sixteen colors. The VIC signal is available 
at RF levels at the RF modulator output and at analog levels at the 8 pin DIN monitor connector. 



RF Modulator 



The modulator provides a broadcast type RF signal carrying the VIC composite video and audio 
signals. The NTSC modulator is switchable between channels 3 and 4 to help minimize local broad- 
cast interference. The signal generated by the RF modulator complies with FCC ruling concerning FCC 
Class B, TV interface devices. The RF output is accessible via a standard RCA type phone/video jack. 



Monitor Output 




Pin 


Signal 


Description 


1 


LUM/SYNC 


Lumlnance/SYNC Ouput 


2 


GND 




3 


AUDIO OUT 




4 


VIDEO OUT 

AAA ^^^k A ^^^k A ^ A 


Composite signal output 


5 


AUDIO IN 




6 


COLOR OUT 


Chroma signal output 


7 


NC 


No connection 


8 


NC 


No connection 



The VIC video output provides the following signals: 



Signal 



Level 



Impedance 



DC Offset 



Luminance/Sync 
Chroma 
Composite 
Audio 



1 Vp-p 

1 Vp-p 

1 Vp-p 

1 Vp-p 



75 n 

75 Q 

75 fl 

IK 



0.5 V 
0.5 V 
0.5 V 



31 



THE VIDEO INTERFACE (Continued) 



The RGBI Video Interface 



The 8563 video interface signal, for 80 column display in sixteen colors, is available at digital levels 
for RGBI and at a three-level derived analog for black and white composite video. 



Monitor Output 




2 3 4 



5 



o o o o o 



o o o o 



6 



8 9 




CN10 



Pin 


Signal 


1 


Ground 


2 


Ground 


3 


Red 


4 


Green 


5 


Blue 


6 


Intensity 


7 


Monochrome 


8 


Horizontal Sync 


9 


Vertical Sync 



The 8563 output provides the following signals: 



Signal 



Level 



Impedance 



Red 
Green 

Blue 

Intensity 

HSync 

VSync 

Composite 

Full Intensity 
Half Intensity 
Sync 



TTL 
TTL 
TTL 
TTL 
TTL 
TTL 



TTL 

TTL 

TTL 

TTL 

TTL 

TTL 
75Q 



2.0V 
1.5V 
0.5V 



32 



THE 8564 VIDEO INTERFACE CHIP 




The 8564 VIC chip used in the CI 28 is an updated version of the VIC chip used in current C64 
systems. It contains all of the video capabilities of the earlier 6567 VIC chip, including high resolution 
bit mapped graphics and movable image blocks. It also supports new features used by the CI 28 system, 
including extended keyboard scanning. Its register map is upward compatible with the old VIC, allowing 
compatibility in C64 mode. It is powered by a single 5V DC source, instead of the two sources re- 
quired by the old VIC chip. 

Summary of functions that remain the same as the 6567 VIC: 



Standard Color Character Display Mode 



Multicolor Character Display Mode 
Extended Color Character Display Mode 



Standard Bit Map Mode 



Multicolor Bit Map Mode 



Movable Image Blocks 

Movable Image Block Magnification 



Movable Image Block Priority 

Movable Image Block Collision Detection 

Screen Blanking 

Row/Column Display Select 

Smooth Scrolling 

Light Pen 

Raster Compare Interrupt 



As these functions exist in the previous VIC, their description is purposely kept to a minimum. The 
new functions, however, are described in detail below. Additional Functions of 8564 VIC: 



Extended Keyboard Scanning 

The 8564 contains a register called the Keyboard Controi Register. This register allows scanning 
of three additional keyboard control lines on the CI 28 keyboard. Thus, the CI 28 keyboard can have 
advanced additional keys in CI 28 mode, while still retaining complete C64 keyboard compatibility 
in C64 mode. In this register, register 47, bits 0-2 are directly reflected in output lines Kq to K2, while 
bits 3-7 are unused, returning high when read. 



2 MHz Operation 

The VIC chip contains a register which allows the CI 28 system to operate at 2 MHz instead of 
the standard 1 MHz of the C64. This operating speed, however, disallows the use of the VIC chip 
as a display processor. This bit is bit zero in register 48, and setting this bit enables 2 MHz mode. 
During 2 MHz operation, the VIC is disabled as a video processor. The ^Processor spends the cycle 
full time on the bus, while VIC is responsible only for dynamic RAM refresh and DMA arbitration. 
Clearing this bit will bring back 1 MHz operation and allow the use of the VIC as a video display chip. 
During refresh and I/O access, the system clock is forced to 1 MHz regardless of the setting of this bit. 

Bit one of this register contains a chip testing facility. For normal operation this bit must be clear. 
None of the other bits in this register are connected. 



33 



THE 8564 VIDEO INTERFACE CHIP (Continued) 



System Clock Control 

The new VIC chip generates several clocks used by the CI 28 system. The main clock is the 1 MHz 
clock, which operates at approximately 1 MHz at all times. Most bus operations and all I/O operations 
take place in reference to this clock. The next clock to consider is the 2 MHz clock. This clock clocks 
selected syst em com ponents, such as the processor, at 2 MHz when in 2 MHz mode. The VIC chip 

monitors the lOACC input, which indicates the access of an I/O chip, and when asserted, will stretch 

the 2 MHz clock to synchronize all 2 MHz parts with the 1 MHz I/O parts. Finally, the last clock is 
the Z-80 clock, which is a 4 MHz clock that only takes place during the low half of the 1 MHz clock. 

One final note is that since I/O parts look only at the 1 MHz clock, all I/O timings remain the same 

no matter what the 2 MHz clock is doing. 



DMA and Bus Arbitration 



True DMA of the internal processor can now be accomplished by requesting the DMA through VIC. 
The VIC will shut down the processor in an orderly fashion, instead of a suicidal fashion. A DMA 
source requests a DMA via the DMARQST input. VIC will respond to that request with a DMAACK 
after shutting down the processor. The DMA source must listen to the DMAACK line and be prepared 
to itself be shut down in the event that VIC decides to do its own DMA. Thus, the VIC chip has the 
highest DMA priority. The CI 28 system does not use this DMA arbitration scheme, but a fatal DMA 
scheme similar to that of the C64. 



34 



THE 8564 VIDEO INTERFACE CHIP (Continued) 



1-7,47 DB0-DB7 



315009 
8564 VIDEO INTERFACE CHIP 



DB6 
DB5 
DB4 
DBS 
DB2 
DB1 
DBO 




DMARQST 



AEC 
CS 

R/W 



DMAACK 

COLOR 

SYNC 

1MHZ 

RAg" 

CAS 

MUX 

I/O ACC 

2MHZ 

VSS 



1 


48 


2 


47 


3 


46 


4 


45 


5 


44 


6 


43 


7 


42 


8 


41 


9 


40 


10 


39 


1 1 8564 38 


12 VIC 37 


13 


36 


14 


35 


15 


34 


16 


33 


17 


32 


18 


31 


19 


30 


20 


29 


21 


28 


22 


27 


23 


26 


24 


25 



vcc 

DB7 

DBS 

DBS 

DB10 

DB11 

A10 

A9 

A8 

A7 

A6 (1) 

A5 (A13) 

A4 (A 12) 

A3 (All) 

A2 (AlO) 

A1 (A9) 

AO (A8) 

All 

PH IN 

PH CL 

K2 

K1 

KO 

Z80 



8 



10 



11 



12 



13 



14 



15 



16 



17 

18 

19 
20 
21 

22 

23 



30 



31 
32-37 



IRQ 



LP 



BA 



DMARQST 



AEC 



CS 



R/W 



DMAACK 



COLOR 



SYNC 

1MHz 

RAS 
CAS 
MUX 

I/O ACC 

2MHz 



24 


VSS 


25 


Z80 PHI 


26-28 


K0-K2 


29 


PH CL 



PH IN 



All 
A0-A5 



38, 39 A6, A7 
31, A8-A11 
40-42 



43-46 DB8-DB11 



47 
48 



DB7 
VCC 



These are the bidirectional Data Bus signals. 
They are for communication between the VIC 
and the processor, and can only be accessed 
during AEC high. 

Interrupt output. Generates a low interrupt 

signal. 

Light Pen. Edge triggered latch for light pen 

input. 

Bus Available output. Used to DMA the 

processor. 

External DMA request input. Pulled high on 

the CI 28. 

Address Enable Control output. Goes high for 

processor enable on the shared bus, low for 

VIC cycle and VIC or external DMA. 

Chip select input. A low signal selects the 

VIC chip. 

Standard 8502 bus Read/Write for interface 

between the processor and the various VIC 

registers. 

External DMA Acknowledge. Not used in the 

CI 28 design. 

Output containing all color based video infor- 
mation: chrominance, color reference burst, 
and color of display data. 
Output containing composite sync informa- 
tion, video data, and luminance information. 
The 1MHz system clock. All system bus 
activity is referenced to this clock. 
Row Address Strobe output for DRAMS. 
Column Address Strobe output for DRAMS. 
Address Multiplexing control output for 
DRAMS. 

Input from the PLA, indicating an I/O chip ac- 
cess for clock stretching. 
This is the changing system clock, which will 
be either 1MHz or 2MHz. If the 2MHz bit is 
clear, no VIC or external DMA is taking 
place, and no I/O operation is occurring, the 
clock will be 2MHz. It will be 1MHz 
otherwise. 
Ground. 

The special 4MHz Z-80 clock. 
Extended keyboard strobe bits. 
The Color Clock input, used to derive the 
chroma signal, 14.31818 MHZ NTSC. 
The fundamental shift rate clock input, also 
called the DOT clock. Used as the reference 
for all system clocks. Determines the dot 
transfer rate to the display. 
See A8-A11 below. 

Multiplexed Address Lines. During row ad- 
dress time, Aq - A5 are driven on Ao - A5. 
During column address time, Ag - A13 are 
driven on Aq - A5 and Aq is held at one. 
During a processor write or read, Ao - A5 
serve as ad dress inputs which latch on the 
low edge of RAS. 
Used as VIC address lines. 
Static Address lines. These address lines 
are used for non-multiplexed VIC memory 
accesses, such as to Character ROM and Col- 
or RAM. 

These are the extended data bus signals. 
They are used for VIC communication with 
the Color RAM. 
See Pins 1-7, 47, DB0-DB7. 
5VDC input. 



35 



THE 8563 VIDEO CONTROLLER 



1*' 



(■_ 



A ^ ' ^ J 






■^ ^ 



. ^ 



^ ^ > 



^ ^ 



-rC 



^^ 



^ ^ 



A^^ ^ ■-" 



r^ ■_ 



^ h >. ■■ 



Fin.D OUT SCHfiMATlC SHEET 3, PAGE 75/ FOR EASY REFERENCE. 



-. •. -^r 






J ' , 



.-^" 



The 8563 is a HMOSII technology, custom, 80 column, color video display controller. The 8563 
supplies all necessary signals to directly interface to 16K of DRAM, including refresh, and generates 
RGBI for use with an external RGBI monitor. 



RESET 




Do- D7 




CS 
CS 

RS 



R/W 




C 
E 



DISPLAY RAM 




DISPLAY 
ENABLE 




HSYNC 
VSYNC 




DCLK 
CCLK 

LPEN 
R 

G 

B 

I 



There are many different signals involved with the 8563 chip, but they can generally be divided 
into three categories. The CPU Interface signals serve as an interface to the 8502 bus. The Local 
Bus Management signals serve to maintain the local memory bus. Finally, the Video Interface signals 
are those signals that are necessary to provide an RGBI image on an RGBI monitor. 

The 8563 chip interfaces directly to the 8502 bus using a minimum of signals. This is due mainly 
to the local memory used by the 8563. 

The Local Bus Management Interface is a group of signals generated by the 8563 for the manage- 
ment of local video DRAM. This local DRAM both simplifies the addition of an 80 column video display 
to the system and enables it to support an 80 column display without taxing its memory resources. 

The final set of 8563 signals are the Video Interface signals. These signals are directly related to 
the displayed video image. 



36 



THE 8563 VIDEO CONTROLLER (Continued) 



External Registers 

The 8563, which sits at $D600 in the CI 28, appears to the user as a device consisting of only 
two registers. These two registers are indirect registers which must be programmed to access the 
internal set of thirty-seven programming registers. The first register, located at $D600, is called the 
Address/Status register. When written to, the five least significant bits convey the address of an in- 
ternal register to be accessed in some way. On a read of this register, a status byte is returned. Bit 
7 of this register is low while display memory is being updated, and goes high when ready for the 
next operation. The 6th bit will return low for a light pen register invalid condition and high for a valid 
light pen address. The final register indicates with a low that the scan is not in vertical blanking, high 
that it is in vertical blanking. 

The other register is the data register. It can be read and written to. Its purpose is to write data 
to the internal register selected by the Address register. All internal registers can be read and written 
to through this register, though not all of them are a full eight bits wide. 

Internal Registers 

I here are thirty-seven internal registers in the 8563, used for a variety of operations. They fall into 
two basic groups — setup registers and display registers. Setup registers are used to define internal 
counts for proper video display. 

The display registers are used to define and manipulate characters on the screen. Once a character 
set has been downloaded to the chip, it is possible to display 80 column text in 4-bit digital color. 
There are also block movement commands that remove the time overhead needed to load large amounts 
of data to the chip through the two levels of indirection. Below is a display of the 8563 internal register 
map. 



Bit 7 



Bite 



Bi I 5 



Bit 



RDQ 



Bi t 



Bit 2 



Bi t 1 



Bi t Q 



Hop 1 zon to 1 To to 1 



RQl 



Horizontol Dlspioyed 



RQ2 



RQ3 



Ver t i CO 1 Sync N 1 d t h 



Horizontal Sync PositJo 



n 



Horizontol 3unc Width 



RB4 



Verticol Totol 



RG5 



iui.u.iui.njijjjuijiji.ii,u.ii. 



'.ll.IUi.lt JiiUi.ll.ll.H ,l!i lif.il.ll,l/,ll. 






RG6 



Verticol Dlsployed 



Verticol Totol Pdjust 



RQ7 



Venticel 5unc Positio 



RGB 



RG9 



^\■\^^nl■\^n^^^^l^lv^l^l^^^l^^■^^^^^nnn\v^l■M'\^^n^^^n^^^^nn^^^^^^m^nv 

HtMIMIi H HWIwit m ii m ii n iii mn miHi mm ii4iiiii nm iiiM<i mn iiiiii m i H i m iiijiii iMMMM JLilJ i i 






June ros 1 Lion 

ii.u.irijhiuuuuiiJ.imiJJi.i J.\j.u.u.ujj.ii.iuuj.uM^^ 




44W 



M 



UjJJJJJJJJJ.lJJUUiMMJlJiJIJIJUiJiJUl.ilMJJ. 



a 



^TT- ( ' l('(l ' (< ' (<4(i4(< ' (< ' (< ' (<M ' iv\v\\ ' iv ' t^ ' i\V\ ' !\ ' ^nnnv\v» ' S\ 

^' L uriuuuui.ii.iui.iui\uui.tuui.ii.ii.ii.n.i i.iiiuuuuuuuui.is.ii.ii 



R12 



R13 



R14 



R15 



R16 



R17 



RJ8 



R19 



R20 



R21 



n22 



R23 



R24 



R25 



R26 



R27 



R28 



R29 



R3Q 



R31 



R32 



R33 



R34 



R35 



R36 



or oc 
Cursor 



u.ti.tu. 
ter 



olol 



Interloce Mode 
Ver t icol 



ui.{t.u.ux 

DispIoLj Stort Hddress 

Display 5 tor t Pddress 



or L Dcon Line 
Cur Vor Fnd Scon 



ri 



ng 



RT^TTF 
Low) 



Cursor Position (High 
Cursor Ros i t i on [Low) 



Light Pen Ver t Icol 



Light Pen Hor i zon to I 
Updo te Loco t i on (H i ghl 



Updo t e Co c o t i on [L ow 



Httribule Start MdJF^¥F (High] 

"nil FTbuie stort Rddress ~rr5"jr 



Lhor oc ten 

nnnnnnnnnvmr 



r^!^iimvf 



opy 
Groph/Tex t 



o to 1 -Hop 1 zori to 1 



UUUUUJAiAUULli.li 



Rev Screen 

Fitrb Enb 



rrnnvmnrmrmvm 

Brink Rote 



Choroc ter Dl sployed-Horj zonlol 
Chor oc ter Ui sployed-Ver t icol 
Ver 1 1 c o"I Snoo th Scrol 1 ^^ 



Sen i groph P 1 x Db 1 



Hor i zon to I Snoo th Scrol 1 



Foreground Co I or 



Bock ground Color 



flddr ess I nc r en©n t per Row 



Choroc ter 5e t Hddress 






4 1 O 4 / 4 4 1 O hAUUiAUUiAJAUitiAlhliAJAUUU^^ 



lUJAiAJJUIMAjJUUiJim 

Under line S 



con 



r 



1 ne 



Word Coun t tcoun t- 1 
CPU Heod/Wri te Uott 



B I ock Copy Source Hddress ^H 1 gh 



B 1 ock Copy Source Address f Lon 
D i s p 1 o y 



Enob 1 e Beg i n 
1 sp" Toy TrToFTe End 



UALUAUiilALUAUUl 



ULUJLILUMMJUlJUWJLillJMJULiL^ 



DRHM Refresh per Scon Li ne 



8563 REGISTER MAP 



37 



8563 VIDEO CONTROLLER (Continued) 



315014 
8563 CRT VIDEO CONTROLLER 



CCLK- 


1 


48 


DCLK- 


2 


47 


HSYNC- 


3 


46 


CS- 


4 


45 


nc- 


5 


44 ■ 


nc- 


6 


43 


CS- 


7 


42 


RS- 


8 


41 


R/W- 


9 


40 


D7- 


10 8563 


39 


D6- 


11 CRT 


38 


VSS- 


1 2 CNTRL 


37 


D5- 


13 


36 


D4- 


14 


35 


D3- 


15 


34 


D2- 


16 


33 


D1- 


17 


32 


DO- 


18 


31 


DISPEN- 


19 


30 


VSYNC- 


20 


29 


DR/W- 


21 


28 


INIT- 


22 


27 


Res- 


23 


26 


TEST- 


24 


25 



CAS 

RAS 

R 

G 

B 

I 

DD7 

DD6 

DD5 

DD4 

DD3 

VDD 

DD2 

DD1 

DDO 

DA7 

DA6 

DA5 

DA4 

DA3 

DA2 

DAI 

DAO 

LPEN 



1 


CCLK 


2 


DCLK 


3 


HSYNC 


4 


CS 


5,6 


NC 


7 


CS 


8 


RS 



9 



R/W 



10,11, 


D0-D7 


13-18 




12 


VSS 


19 


DISPEN 


20 


VSYNC 


21 


DR/W 


22 


INIT 


23 


RES 


24 


TEST 


25 


LPEN 



Character Clock output. 

Video Dot Clock D. 

Horizontal Sync Signal. 

Chip Select input, active high. 

No Connection. 

Chip Select input, active low. 

Register Select input. A high allows reads & 

writes to the selected data register. A low 

allows reads of the Status register and writes 

to the Address register. 

The read/write line controls the data direction 

for the data bus. Read is active high, write is 

active low. 

Bi-directional data bus. 

Ground. 

Display Enable output. 
Vertical Sync signal. 
Local Display DRAM Read/Write. 
Active low input for clearing internal control 
latches. 

Reset Input that initializes all internal scan 
counters, but not control registers. 
Used for testing only — tied to ground. 
Input for Light Pen. A positive going transition 
on this input latches the vertical and horizon- 
tal position of the character being displayed at 
that time. 
Local display DRAM address bus. 



26-33, DA0-DA7 

34-36, DD0-DD7 Bidirectional local display DRAM data bus. 

38-42 

37 

43-46 



VCC 
R,G,B,I 



47 
48 



RAS 
CAS 



5VDC input. 

Pixel Data Outputs. A four-bit code is formed, 
associated with each pixel, containing col- 
or/intensity information, allowing a total of 16 
colors on grey shades to be displayed. 
Row Address Strode for local DRAM. 
Column Address Strobe for local DRAM. 



906112 
6581 SOUND INTERFACE 

DEVICE (SID) 



CAP 
CAP 
CAP 
CAP 




02- 
R/W- 

AO- 
A1- 
A2- 
A3- 
A4- 
GND- 



1A 




28 


IB 




27 


2A 




26 


2B 




25 


CJl 




24 


6 




23 


7 


6581 


22 


8 


SID 


21 


9 




20 


10 




19 


11 




18 


12 




17 


13 




16 


14 




15 



VDD 
A. OUT 
EXT IN 
VCC 
POTX 
POT Y 

D7 
D6 
D5 
D4 
D3 
D2 
Dl 
DO 



1,2, 
3,4 


CAP1A,1B 
2A,2B 


Capacitor filter connections. 


5 


RES 


Reset input. A low pulse initializes the SID. 


6 


02 


Processor phase 2 clock input. 


7 


R/W 


Processor read/write input. 


8 


CS 


Chip select input. 


9-13 


A0-A4 


Address lines from processor. 


14 


GND 


Dc ground connection. 


15-22 


D0-D7 


Data Bus connections. 


23 


POT Y 


Input to a A/D converter used to detect the 
value of a variable resistor. Commonly con- 
nected to game paddles. 


24 


POT X 


Same as POT Y. 


25 


VCC 


5VDC input. 


26 


EXT IN 


External audio input. 


27 


Audio out 


Audio output, AC coupled to audio amp. 


28 


VDD 


12VDC input. 



38 



IC 8568 

80 COLUMN CRT CONTROLLER 

PN #315092-01 



This Circuit implements the features of the 6545E CRT Controller with additional features to increase 
system integration. 



Features 



Single +5 volt power supply. 
Interlaced or non-interlaced display. 
NTSC or PAL operation. 

Shared RAM for Character Data, Pointers and 
Attributes. 

Cursor and Attributes decoded on-chip. 

R, G, B, I pixel outputs. 

Separate programmable Horizontal and Vertical 

Sync outputs. 

Character Clock generated on-chip. 

Interfaces to DRAMs with on-chip RAS/CAS 

timing. 

Programmable character fonts. 
Programmable frame height, width and rate. 
Directly interfaces to 4164 or 4416 DRAMs. 



CAS 

CCLK 

DCLK 

HSYNC 

CS 

CS* 

RS 

R/W 

INTR 

D7 

D6 

Vss 

D5 

D4 

D3 

D2 

D1 

DO 

CSYNC 

VSYNC 

DR/W 




INIT 
TEST 



1 


48 


2 


47 


3 


46 


4 


45 


5 


44 


6 


43 


7 


42 


8 


41 


9 


40 


10 


39 


11 


38 


12 


37 


13 


36 


14 


35 


15 


34 


16 


33 


17 


32 


18 


31 


19 


30 


20 


29 


21 


28 


22 


27 


23 


26 


24 


25 



RAS 

CV 

R 

G 

B 



DD7 

DD6 

DD5 

DD4 

DD3 

Vcc 

DD2 

DD1 

DDO 

DA7 

DA6 

DA5 

DA4 

DA3 

DA2 

DAI 

DAO 

LPEN 



The device is a highly integrated text display chip designed to reduce the parts count of an 80-column 
display system. The CRT Controller contains the high-speed pixel frequency logic, requiring only a buf- 
fer to drive low impedance loads. The CRT Controller is capable of addressing 64K of DRAM memory 
for Character Data (character fonts). Character Pointers and Attributes. In addition, the DRAM signals 
RAS, CAS, Read/Write, Data and Multiplexed Addresses are generated on-chip and require no exter- 
nal logic to interface to the DRAMs. The DRAM multiplexed Addresses can be configured via a pro- 
grammable register bit to interface directly to either 4164 or 4416 Type DRAMs 

The device contains an internal 80-column double line buffer. This buffer is loaded with Character Pointers 
and Attributes during the Horizontal-Blanking interval (and any blank scan lines). These Pointers and 
Attributes are loaded during one displayed character row for use in the next character row. This device 
is equivalent to a 2568 or 8568. 

The -01 version of the part is intended for use in systems with a TTL level Dclk signal. The -02 version 
is for systems with a CMOS level Dclk. 



39 



PIN DESCRIPTION 



CPU INTERFACE 



D0-D7 
CS 
CS* 
RS 



R/W 



INTR 



Bidirectional Data Bus interface to the CPU. 

Chip Select input (active high). 

Chip Select input (active low). 

Register select input. A high allows reads and writes of the selected data register. A 
low allows reads of the Status Register and writes of the Address Register. 

Read/write input to control D0-D7 data direction. A high allows the CPU to read data 
supplied by the CRT Controller. A low allows the CRT Controller to accept data written 
by the CPU. 

Interrupt request output. An open-drain output that is driven low when the Update Ready 
status bit makes a *zero' to *one' transition. This output goes high-impedance when 

either the Update Ready status bit is a *zero' or the CPU reads the status register. 



VIDEO INTERFACE 



Vcc 
Vss 
RES 



LPEN 



DCLK 



HSYNC 
VSYNC 
CSYNC 



R, G, B, 



CV 

DR/W 

DD0-DD7 

DA0-DA7 

RAS 

CAS 

CCLK 

INIT 



TEST 



5 VDC +/-5% 
VDC 

Reset input to initalize all internal scan counter circuits. The control registers are not 
affected. RES can be used to synchronize the display frame to an externally generated 
signal. This signal should not be confused with the INIT input. 

Light pen input. A low-to-high transition of the LPEN input loads the internal light pen 
registers with the vertical and horizontal character poisitions. 

Dot clock input. Determines the pixel width, DCLK is divided internally to generate the 
internal character clock and DRAM signals. 

Horizontal sync output. HSYNC polarity, position and duration are fully programmable. 

Vertical sync output. VSYNC polarity, position and duration are fully programmable. 

Composite SYNC output. This is the logical exculsive-nor of internal active-high HSYNC 
and VSYNC signals. 

Red, Green, Blue and Intensity outputs. These output a four-bit code associated with 
each pixel. A total of 16 colors (or shades of gray) may be displayed. 

Composite Video output. This is the logical OR of the R, G, and B outputs. 

Video Display RAM read/write output signal. 

Video Display RAM bidirectional Data Bus. 

Video Display RAM multiplexed Address Bus outputs. 

Row Address Strobe output for the multiplexed addresses. 

Column address strobe output for the muliplexed addresses. 

Character clock output (for unspecified uses). 

Initialization input pin (active low). Clears internal control latches, allowing the CRT 
Controller to begin proger operation following power-on initialization. The INIT pin should 
be held low for at least 16 DCLK cycles during system initialization, and held high dur- 
ing operation. 

This pin reconfigures the part to simplify automatic testing. In normal use this pin should 
be connected to Vss. 



40 



8580 SID 

Part 0318013-01 



The SID consists of three synthesizer ^'voices" which can be used independently or in conjunction with 
each other (or external audio sources) to create complex sounds. Each voice consists of a Tone 
OscillatorAA/aveform Generator, and an Envelope Generator and an Amplitude Modulator. The Tone 
Oscillator controls the pitch of the voice over a wide range. The Oscillator produces four waveforms 
at the selected frequency, with the unique harmonic content of each waveform providing simple control 
of tone color. The volume dynamics of the oscillator are controlled by the Amplitude Modulator under 
the direction of the Envelope Generator. When triggered, the Envelope Generator creates an amplitude 
envelope with programmable rates of increasing and decreasing volume. In addition to the three voices, 
a programmable Filter is provided for generating complex, dynamic tone colors via subtractive synthesis. 



SID allows the microprocessor to read the changing output of the third Oscillator and third Envelope 
Generator. These outputs can be used as a source of modulation information for creating vibrato, fre- 
quency/filter sweeps and similar effects. The third oscillator can also act as a random number generator 
for games. Two A/D converters are provided for inter-facing SID with potentiometers. These can be 
used for *'paddles*' in a game environment or as front panel controls in a music synthesizer. SID can 
process external audio signals, allowing multiple SID chips to be daisy-chained or mixed in complex 
polyphonic systems. 



A4 A3 K2 



AO C5 R/W 02 RES 



CHIP ACCESS CONTROL 







TONE 
OSCILLATOR/ 

WAVEFORM 
GENERATOR i 



\ 



ENVELOPE 
GENERATOR I 






TONE 
OSCILLATOR/ 

WAVEFORM 
GENERATOR Z 






ENVELOPE 
GENERATOR 2 



< 



\ 



TONE 
OSCILLATOR/ 

WAVEFORM 
GENERATOR 3 




ENVELOPE 
GENERATOR 3 



/^\ 




NOISE 



AMPLl TUDE 

MODULATOR 







FLTL 

NOISE 



AMPLITUDE 

MODULATOR 

2 



T 





3 OFF 



/\/\ 



FLTL 

NOISE 



AMPLITUDE 

MODUL ATOR 

3 



F IL T.3 




\Z. 



FILTER 



CAP2B 



CAP2A 



C APlB 



CAPIA 



1/NJ 




POTS 



POT Y 



POT Y 



EXT IN 



SID BLOCK DIAGRAM 



41 



SID PIN DESCRIPTION 



CAP1A 

CAP1B 

CAP2A 

CAP2B 

RES 

(32 

RA/V 

CS 

AO 

A1 

A2 

A3 

A4 

GND 



1 


28 


2 


27 


3 


26 


4 


25 


5 


22 


6 


23 


7 SID 22 1 


8 


21 


9 


20 


10 


19 


11 


18 


12 


17 


13 


16 


14 


15 



Vdd 

AUDIO OUT 

EXT IN 

Vcc 

POTX 

POT Y 

D7 

D6 

D5 

D4 

D3 

02 

D1 

DO 



CAPIA, CAPIB (Pins 1,2)/CAP2A, CAP2B (Pins 3,4) 

These pins are used to connect the two intergrating capacitors required by the programmable Filter. 
C1 connects between pins 1 and 2, C2 between pins 3 and 4. Both capacitors should be the same 
value. Normal operation of the Filter over the audio range (approximately 30Hz-12KHz) is accomplished 
with a value of 6800 pF for C1 and C2. Polystyrene capacitors are preferred. The frequency range 
of the Filter can be tailored to specific applications by the choice of capacitor values. For example, 
a low-cost game may not require full high-frequency response. In this case, larger values for C1 and 
C2 could be chosen to provide more control over the bass frequencies of the Filter. The approximate 
maximum Cutoff Frequency of the Filter is given by: FCmax = 8.2E-5/C 
Where C is the capacitor value. The range of the Filter extends approximately 9 octaves below the 

maximum Cutoff Frequency. 

Res (Pin 5) 

This TTL-level input is the reset control for SID. When brought low for at least ten 02 cycles, all inter- 
nal registers are reset to zero and the audio output is silenced. This pin is normally connected to 
the reset line of the microprocessor or a power-on-clear circuit. 

02 (Pin 6) 

This TTL-level input is the master clock for SID. All oscillator frequencies and envelope rates are 
referenced to this clock. 02 also controls data transfers between the SID and the microprocessor. 
Data can only be transferred when 02 is high. Essentially, 02 acts as a high-active chip select as 
far as data transfers are concerned. This pin is normally connected to the system clock, with a nor- 
mal operating frequency of 1.0MHz. 

R/W (Pin 7) 

This TTL-level input controls the direction of data transfers between SID and the microprocessor. 
If the chip select conditions have been met, a high on this line allows the microprocessor to Read 
data from the selected SID register and a low allows the microprocessor to Write data into the selected 
SID register. This pin is normally connected to the system ReadA/Vrite line. 

08 (Pin 8) 

This TTL-level input is a low active chip select which controls data transfers between SID and the 
microprocessor CS must be low for any transfer. A Read from the selected SID register can only 
occur if CS is low, 02 is high and R/W is low. This pin is normally connected to address decoding 
circuitry, allowing SID to reside in the memory map of a system. 



42 



SID PIN DESCRIPTION (Continued) 



A0-A4 (Pins 9-13) 

These TTL-level inputs are used to select one of the 29 SID registers. Although enough addresses 
are provided to select 1 of 32 registers, the remaining three register locations are not used. A Write 
to any of these three locations is ignored and a Read returns invalid data. These pins are normally 
connected to the corresponding address lines of the microprocessor so that SID may be addressed 
in the same manner as memory. 

GND (Pin 14) 

For best results, the ground line between SID and the power supply should be separate from the 
ground lines to other digital noise at the audio output. 

D0-D7(Pins 15-22) 

These bidirectional lines are used to transfer data between SID and the microprocessor. They are 
TTL compatible in the output mode and capable of driving 2 TTL loads in the output mode. The data 
buffers are usually in the high-impedance off state. During a Write operation, the data buffers remain 
in the off (input) state and the microprocessor supplies data to SID over these lines. During a Read 
operation, the data buffers turn on and SID supplies data to the microprocessor over these lines. 
The pins are normally connected to the corresponding data lines of the microprocessor. 

POTX, POTY (Pins 24, 23) 

These pins are inputs to the A/D converters used to digitize the position of potentiometers. The con- 
version process is based on the time constant of a capacitor tied from the POT pin to ground, charged 
by a potentiometer tied from the POT pin to +5 volts. The component values are determined by: 
RC = 1.04E-3 

Where R is the maximum resistance of the pot and C is the capacitor. The larger the capacitor, the 
smaller the POT value jitter. The recommended values for R and C are 470K Ohms and 2200 pF. 
Note that a spearate pot and cap are required for each POT pin. 

Vcc (Pin 25) 

As with the GND line, separate +5 VDC line should be run between SID Vcc and the power supply 
in order to minimize noise. A bypass capacitor should be located close to the pin. 

Ext In (Pin 26) 

This analog input allows external audio signals to be mixed with the audio output of SID or processed 
through the Filter. Typical courses include voice, guitar and organ. The input impedence of this pin 
is in the order of 100K Ohms. External input amplitude should not exceed 3 volts p-p. 
Due to the DC level at the external input pin, external signals should be AC-coupled to EXT IN by 
an electrolytic capacitor in capacitor in the 1-10/iF range. As the direct audio path (FILTEX = 0) has 
unity gain, EXT IN can be used to mix outputs of many SID chips by daisy-chaining. The number 
of chips that can be chained in this manner is determned by the amount of noise and distortion allowable 
at the final output. Note that the output Volume control will affect not only the three SID voices, but 
also any external inputs. 

Audio Out (Pin 27) 

This open-source buffer is the final audio output of SID, composed of the three SID voices, the Filter 
and any external input. The output level is set by the output Volume control and reaches a maximum 
of approximately 3 volts p-p at a 4.75 VDC level. 

The output of SID rides on a 4.75 level, it should be AC-coupled to any audio amplifier with an elec- 
trolytic capacitor in the 1-10/xF range. 

Vdd (Pin 28) 

As with Vcc, a separate + 9 VDC line should be run to SID Vdd and a bypass capacitor should be used. 



43 



EQUAL-TEMPERED MUSICAL SCALE VALUES 



The following table lists the numerical values which must be stored in the SID Oscillator frequency control registers to produce the notes 
of the equal-tempered musical scale. The equal-tempered scale consists of an octave containing 12 semitones (notes): C. D, E, F, G, A, 
B and C*,D*,F*,G*,A*. The frequency of each semitone is exactly the 12th root of 2 ( 12 VT) times the frequency of the previous semitone. 
The table is based on a 02 = clock of 1 .0 MHz. Refer to the equation given in the Register Description for use of other master clock frequen- 
cies. The scale selected is concert pitch, in which A4-440 Hz. Transpositions of this scale and scales other than the equal-tempered scale 
are also possible. 



Musical 


Freq. 


Osc. Fn. 


Osc. Fn. 


Musical 


Freq. 


Osc. Fn. 


Osc. Fn 


Note 


(Hz) 


(Decimal) 


(Hex) 


Note 


(Hz) 


(Decimal) 


(Hex) 


OCO 


16.35 


274 


0112 


48 04 


261 .63 


4389 


1125 


1 00$ 


17.32 


291 


0123 


49 04$ 


277.18 


4650 


122A 


2 DO 


18.35 


308 


0134 


50 D4 


293.66 


4927 


133F 


3D0$ 


19.44 


326 


0146 


51 D4$ 


311.13 


5220 


1464 


4E0 


20.60 


346 


01 5A 


52 E4 


329.63 


5530 


159A 


5 FO 


21.83 


366 


01 6E 


53 F4 


349.23 


5859 


16E3 


6F0$ 


23.12 


388 


0184 


54 F4$ 


370.00 


6207 


183F 


7 GO 


24.50 


411 


01 8B 


55 G4 


392.00 


6577 


1981 


8G0$ 


25.96 


435 


01 B3 


56G4$ 


415.30 


6968 


1838 


9 AO 


27.50 


461 


01OD 


57 A4 


440.00 


7382 


1CD6 


10 A0$ 


29.14 


489 


01 E9 


58 A4$ 


466.16 


7821 


1E80 


11 BO 


30.87 


518 


0206 


59 84 


493.88 


8286 


205E 


12 01 


32.70 


549 


0225 


60 05 


523.25 


8779 


224B 


13 01$ 


34.65 


581 


0245 


61 05$ 


554.37 


9301 


2455 


14 D1 


36.71 


616 


0268 


62 D5 


587.33 


9854 


267E 


15 D1$ 


38.89 


652 


0280 


53 D5$ 


622.25 


10440 


2808 


16 El 


41.20 


691 


0283 


64 E5 


659.25 


11060 


2834 


17 F1 


43.65 


732 


02DO 


65 F5 


698.46 


11718 


2D06 


18 F1$ 


46.25 


776 


0308 


66 F5$ 


740.00 


12415 


307F 


19 G1 


49.00 


822 


0336 


67 G5 


783.99 


13153 


3361 


20 G1$ 


51.91 


871 


0367 


68G5$ 


830.61 


13935 


366F 


21 A1 


55.00 


923 


039B 


69 A5 


880.00 


14764 


39AO 


22 A1$ 


58.27 


978 


03D2 


70 A5$ 


932.33 


15642 


3D1A 


23 B1 


61.74 


1036 


0400 


71 B5 


987.77 


16572 


4080 


24 02 


65.41 


1097 


0449 


72 06 


1046.50 


17557 


4495 


25 02$ 


69.30 


1163 


048B 


73 06$ 


1108.73 


18601 


48A9 


26 D2 


73.42 


1232 


04D0 


74 D6 


1174.66 


19709 


40F0 


27D2$ 


77.78 


1305 


0519 


75 D6$ 


1244.51 


20897 


518F 


28 E2 


82.41 


1383 


0567 


76 E6 


1318.51 


22121 


5669 


29 F2 


87.31 


1465 


05B9 


77 F6 


1396.91 


23436 


5880 


30F2$ 


92.50 


1552 


0610 


78F6$ 


1479.98 


24830 


60FE 


31 G2 


98.00 


1644 


0660 


79 G6 


1567.98 


26306 


6602 


32 G2$ 


103.83 


1742 


060 E 


80G6$ 


1661.22 


27871 


6CDF 


33 A2 


110.00 


1845 


0735 


81 A6 


1760.00 


29528 


7358 


34 A2$ 


116.54 


1955 


07A3 


82 A6$ 


1864.65 


31234 


7A34 


35 B2 


123.47 


2071 


0817 


83 B6 


1975.53 


33144 


8178 


36 03 


130.81 


2195 


0893 


84 07 


2093.00 


35115 


8928 


37 03$ 


138.59 


2325 


0915 


85 07$ 


2217.46 


37203 


9153 


38 D3 


146.83 


2463 


099F 


86 D7 


2349.32 


39415 


99F7 


39 D3$ 


155.56 


2610 


0A32 


87D7$ 


2489.01 


41759 


A31F 


40 E3 


164.81 


2765 


OAOD 


88 E7 


2637.02 


44242 


A0D2 


41 F3 


174.61 


2930 


0B72 


89 F7 


2793.83 


46873 


8719 


42 F3$ 


185.00 


3104 


0O20 


90F7$ 


2959.95 


49660 


C1FC 


43 G3 


196.00 


3288 


0008 


91 G7 


3135.96 


52613 


0085 


44G3$ 


207.65 


3484 


0D9O 


92G7$ 


3322.44 


55741 


0980 


45 A3 


220.00 


3691 


0E6B 


93 A7 


3520.00 


59056 


E6B0 


46A3$ 


233.08 


3910 


0F46 


94 A7$ 


3729.31 


62567 


F467 


47 B3 


246.94 


4143 


102F 


95 B7 


3951.06 


66288 


1F2F0 



Although the table above provides a simple and quick method 
for generating the equal-tempered scale, it is very memory 
inefficient as it requires 1 92 bytes for the table alone. Memory 
efficiency can be improved by determining the note value 
algorithmically. Using the fact that each note in an octave 
is exactly half the frequency of that note in the next octave, 
the note look-up table can be reduced from 96 entries to 12 
entries, as there are 12 notes per octave. If the 12 entries 



(24 bytes) consist of the 16-bit values for the eighth octave 
(07 through 87), then notes In lower octaves can be derived 
by choosing the appropriate note In the eighth octave and 
dividing the 1 6-bit value by two for each octave of difference. 
As division by two is nothing more than a right-shift of the 
value, the calculation can easily be accomplished by a sim- 
ple software routine. Although note B7 is beyond the range 
of the Oscillators, this value should still be included in the 



44 



table for calculation purposes (the MSB of B7 would require 
a special soltware case, such as generating this bit in the 
CARRY before shifting). Each note must be specified in a 
form which Indicates which of the 12 semitones is desired, 
and which of the eight octaves the semitone is in. Since four 
bits are necessary to select 1 of 12 semitones and three bits 
are necessary to select 1 of 8 octaves, the information can 
fit In one byte, with the lower nybble selecting the semitone 
(by addressing the look-up table) and the upper nybble be- 
ing used by the division routine to determine how many times 
the table value must be right-shifted. 



SID ENVELOPE GENERATORS 

The four-part ADSR (ATTACK, DECAY, SUSTAIN, 

RELEASE) envelope generator has been proven in electronic 
music to provide the optimum trade-off between flexibility and 
ease of amplitude control. Appropriate selection of envelope 
parameters allows the simulation of a wide range of percus- 
sion and sustained Instruments. The violin is a good exam- 
ple of a sustained instrument. The violinist controls the volume 
by bowing the instrument. Typically, the volume builds slowly, 
reaches a peak, then drops to an intermediate level. The 
violinist can maintain this level for as long as desired, then 
the volume is allowed to slowly die away. A "snapshot" of 
this envelope is shown below: 



PEAK 
AMPLITUDE 



ZERO 
AMPLITUDE 




SUSTAIN 



PERIOD 




INTERMEDIATE 
LEVEL 



This volume envelope can be easily reproduced by the ADSR 
as shown below, with typical envelope rates: 



ATTACK: 
DECAY: 
SUSTAIN: 
RELEASE: 



10 ($A) 500mS 



8 

1 ($A) 
9 



300mS 




750mS 




GATE 




of how it was struck. A typical cymbal envelope is shown 
below: 



ATTACK: 
DECAY: 
SUSTAIN: 
RELEASE 




9 

9 



2mS 
750mS 




750mS 




GATE 



Note that the tone immediately begins to decay to zero 
amplitude after the peak Is reached, regardless of when 
GATE is cleared. The amplitude envelope of pianos and harp- 
sichords is somewhat more complicated, but can be 
generated quite easily with the ADSR. These instruments 
reach full volume when a key is first struck. The amplitude 
Immediately begins to die away slowly as long as the key re- 
mains depressed. If the key is released before the sound has 
fully died away, the amplitude will Immediately drop to zero. 
This envelope is shown below: 



ATTACK: 
DECAY: 
SUSTAIN: 
RELEASE: 




9 





2mS 
750mS 




6mS 




GATE 



Note that the tone decays slowly until GATE is cleared, at 
which point the amplitude drops rapidly to zero. 

The most simple envelope is that of the organ. When a key 
Is pressed, the tone Immediately reaches full volume and 
remains there. When the key Is released, the tone drops 
immediately to zero volume. This envelope Is shown below: 



s 



ATTACK: 



DECAY: 

SUSTAIN: 

RELEASE: 





15 ($F) 




2mS 
6mS 




6mS 




The read power of SID lies in the ability to create original 
sounds rather than simulations of acoustic instruments. The 
ADSR is capable of creating envelopes which do not corres- 
pond to any "real" instruments. A good example would be 
the "backwards" envelope. This envelope Is characterized 
by a slow attack and rapid decay which sounds very much 
like an instrument that has been recorded on tape then played 
backwards. This envelope Is shown below: 



Note that the tone can be held at the intermediate SUSTAIN 
level for as long as desired. The tone will not begin to die 
away until GATE Is cleared. With minor alterations, this basic 
envelope can be used for brass and woodwinds as well as 
strings. 

An entirely different form of envelope Is produced by percus- 
sion instruments such as drums, cymbals and gongs, as well 
as certain keyboards such as pianos and harpsichords. The 
percussion envelope is characterized by a nearly instan- 
taneous attack, immediately followed by a decay to zero 
volume. Percussion instruments cannot be sustained at a 
constant amplitude. For example, the instant a drum is struck, 
the sound reaches full volume and decays rapidly regardless 



ATTACK: 
DECAY: 
SUSTAIN: 
RELEASE: 



10 ($A) 500mS 





15 ($F) 
3 



6m S 




72mS 




GATE 




Many unique sounds can be created by applying the ampli- 
tude envelope of one instrument to the harmonic structure 
of another. This produces sounds similar to familiar acoustic 
instruments, yet notably different. In general, sound is quite 
subjective and experimentation with various envelope rates 
and harmonic contents will be necessary In order to achieve 
the desired sound. 



45 



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46 



FLOPPY DISK DRIVE 

READ/WRITE AMPLIFIER 

Part 0252308-01 



FUNCTIONS 



This is an integrated circuit designed for ReadA/Vrite of Floppy Disk Drive (FDD) 
This IC offers the following features: 

1. Including Head SW Matrix for selecting ReadA/Vrite. 

2. The voltage gain of Pre-Amplifier can be selected to 100 or 200 by connecting the external capacitor. 

3. Peak Shift is less than 1% over Pre-Amplifier input range of 0.25 mVp-p to 10 mVp-p without 
adjustment. 

4. Time Domain Filter contains retriggerable monostable multivibrator which has internal timing 
capacitor allowing to be used only external resistor. 

5. Common, Write and Erase drivers have large current capacities to satisfy versatile FDD's conditions. 

6. Write current can be determined by external resistors and is virtually independent against a change 
of temperature and power supply voltage. 

7. Write current may be selected to two different values by Digital Input signal, if Write current com- 
pensation is required on inner tracks of the disk. 

8. WRITE GATE and ERASE GATE input timings can be set independently. 

9. Power Monitor circuit with Schmitt-Trigger function inhibits illegal writing against power supply voltage 
fluctuation including power ON/OFF transients. 

10. The number of external components is greatly reduced by this one-chip ReadA/Vrite IC. 

Absolute Maximum Ratings (Ta = 25°C) 

Power Supply Voltage Vcc: 17V 

Power Supply Voltage Vcc: 7V 

Digital Signal Inputs (NOTE 1) Input Voltage -0.5 — +5.5V 

POWER ON OUTPUT Voltage Applied 15V 

ERASE OUTPUT Voltage Applied 20V 

COMMON 0. COMMON 1, SOURCE Currents 150mA 

POWER ON OUTPUT SINK Current 20mA 

ERASE OUTPUT SINK Current 150mA 

HEAD oA and oB. HEAD 1A and IB. Voltage Applied 23V 

Operating Ambient Temperature Topr -20 — +75°C 

Operating Junction Temperature Tj + 150°C 



Storage Temperature 



Tstg -65 — +150°C 



NOTE 1: The se inputs are WRIT E CURRENT, WRITE DATA, WRITE GATE, ERASE GATE, SIDE 1. 

and MMVA CONTROL. 



47 



PIN DESCRIPTION 



PIN 


DESCRIPTION 


1 


DIFF CONSTANT B 


2 


DIFF CONSTANT A 


3 


DIFF IN B 


4 


DIFF IN A 


5 


PRE OUT B 


6 


PRE OUT A 


7,8,9 


GAIN SEL A.B.C. 


10 


READ DUMP B 


11 


READ DUMP A 


12 


HEADo A 


13 


HEADo B 


14 


HEAD1 A 


15 


HEAD1 B 


16 


A. GND 


18 


WRITE DUMP A 


19 


WRITE DUMP B 


20 


C0MM0N1 


21 


VCC2 


22 


COMMONo 


23 


E. GND 


24 


ERASE OUT 


25 


W/C COMP 


26 


W/C SET 


27 


WRITE CURRENT 


28 


WRITE DATA 


29 


WRITE GATE 


30 


ERASE GATE 


31 


SIDE 1 


32 


POWER ON 


33 


READ DATA 


34 


MMVA CONT 


35 


VCC1 


36 


MMVS 


37 


MMVA 


38 


D. GND 


40 


MMVA COMP 


41 


COMP IN B 


42 


COMP IN A 


43 


DIFF OUT B 


44 


DIFF OUT A 



FUNCTION 



Connect external components to set the differential constant. 
Differentiator input 

Pre-Amplifier output 

The voltage gain of Pre-Amplifier can be set ot 100 or 200 by connecting 
a capacitor between these pins. 

Connect the head dumping resistor for Read. 

Input and output terminals for ReadAWrite head on Side o- 

Input and output terminals for ReadA/Vrite head on Side 1. 

Analog circuit Ground. 

Connect the head dumping resistor for Write. 

Connect the center tap of ReadA/Vrite head on Side 1. 

12V Power supply terminal. 

Connect the center tap of ReadA/Vrite head on Side o 

Erase circuit Ground. 

Open Collector Erase current output. 

Connect a resistor for Write current compensation. 

Connect a resistor to d etermine Write curre nt. 

Digital input pin. When WRITE CURRENT is set to "L", Write current is 

increased. 

Digtal input pin with Schmitt-Trigged function. When WRITE DATA is set from 

H" to "L'\ Write curre nt is switched. 
Digital input pin. When WRITE GATE is set to "L". Write circuit blocl< 
becomes Active causin g Write curren t to be ON. 
Digital input pin. When ERASE GATE is set to "L", Erase circuit becomes 
Active, causing Erase c urrent t o be ON. 

Digital input pin. When SIDE 1 is set to "L", ReadAA/rite head on Side 1 
becomes Active. 

Open Collector output. When Power Monitor circuit detects the power supply 
voltage drop. POWER ON output is ON. 
Read Data output (Tot em-Pole outpu t). 

Digital input pin. When MMVA CONT is set to '*L", the pulse width of Time 
Domain Filter's mono-muiti is decreased. 
5V Power supply terminal. 

Connect a resistor to determine the pulse width of Read Data output. 

Connect a resistor to determine the pulse width of Time Domain Filter's 

mono-multi. 

Digital circuit Ground. 

Connect a resistor for the pulse width compensation of Time Domain Filter's 

mono-multi. 

Comparator input. 
Differentiator output. 



« ( 



PIN CONFIGURATION 



FDD R/W AMP 

PART #252308-01 



< 



OD 



HEAD 



HEAD 



HEAD 



HEAD 



A.GND 



(NO [F 



WRITE DUMP 



WRITE DUMP 



COMMON 



VCC 



COMMON 



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Q_ 



tn 



Q_ 



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CD 





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C/1 



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44 DIFF OUT A 



43 DIFF OUT B 



42 COMP IN A 



4J]C0MP IN B 



40 MMVA COMP 



39 (NO 



38 D.GND 



37 MMVA 



36 MMVB 



VCC 



34 MMVA CONTROL 



I/O 



INPUT/OUTPUT CIRCUITS 



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906108 
6526 COMPLEX INTERFACE 



vss 

PAO 
PA1 
PA2 
PA3 
PA4 
PA5 
PA6 
PA7 
PBO 
PB1 
PB2 
PB3 
PB4 
PB5 
PB6 
PB7 
PU 
TOD 
VCC 



ADAPTER 



1 


40 


2 


39 


3 


38 


4 


37 


5 


36 


6 


35 


7 


34 


8 


33 


9 


32 


10 6526 31 


1 1 CIA 30 


12 


29 


13 


28 


14 


27 


15 


26 


16 


25 


17 


24 


18 


23 


19 


22 


20 


21 



CNT 

SP 

RSO 

RSI 

RS2 

RS3 

RES 

DBO 

DB1 

DB2 

DBS 

DB4 



1 

2-9 



18 



19 



23 



24 



40 



VSS 
PA0-PA7 



10-17 PB0-PB7 



PC 



TOD 



20 


VCC 


21 


IRQ 


22 


R/W 



cs 



FLAG 



UDO 


25 


02 


DB6 


26-33 


DB0-DB7 


DB7 


34 


RES 


02 


35-38 


RS0-RS3 


FLAG 






CS 






R/W 


39 


SP 


IRQ 







CNT 



Ground Connection. 

Parallel port A signals. Bidirectional parallel 
port. 

Parallel port B signals. Bidirectional parallel 
port. 

Handshake output. A low pulse is generated 
after a read or write on port B. 

Time of day clock input. Programmable 50hz 

or 60hz input. 

5VDC input. 

Interrupt output to microprocessor. 

READ/WRITE input from microprocessor's 
R/W output. 

Chip select input. A low pulse will activate 
CIA. 

Negative-edge sensitive interrupt input. Can 

be used as a handshake line for either parallel 

port. 

02 clock input. 

Bidirectional data bus. 

Low active reset input. Initializes CIA. 

Register select inputs. Used to select all 

internal registers for communications with the 

parallel ports, time of day clock, and serial 

port (SP). 

Serial Port bidirectional connection. An inter- 
nal shift register converts microprocessor 

parallel data into serial data, and visa-versa. 

Count input. Internal timers can count pulses 
applied to this input. Can be used for fre- 
quency dependent operations. 



CASSETTE INTERFACE 



PIN CONFIGURATION 



1 2 3 4 5 6 




A B C D E F 



Pin 


Signal 


A-1 


GND 


B-2 


+ 5V 


C-3 


CASSEI IE MOTOR 


D-4 


CASSEI IE READ 


E-5 


CASSEI IE WRITE 


F-6 


CASSEI IE SENSE 



The Cassette interface is controlled by the 8502 microprocessor. One of the features of the 8502 
is a built-in parallel I/O port (P0-P5). P3 - P5 control most of the cassette interface circuitry, P3, pin 
27 of U6, outputs the write data signal to connector CN2 on pins E and 5. P4 is an input that senses 
the play switch depressed on the cassette deck. P5 is an output that controls the cassette motor. 
When P5 goes "low", pin 1 2 of the inverter U30 goes "high", Q3 is biased on and current is passed 
through the cassette motor coil. U1 is a Complex Interface Adapter (CIA). Parallel ports, serial out- 
puts, and Timers are standard features of the CIA. Read data enters on pins D, 4 of CN2. U1 accepts 
the read data signal on the FLAG input pin 24. 



49 



THE USER PORT 



PIN CONFIGURATION* 



1 2 3 4 5 6 7 8 9 10 11 12 




ABCDEFHJ KLMN 



* See Sheet 1 of Schematic for line definitions. 



Parallel port B of the 6526 CIA device at U4 (PB0-PB7) is made available on the user port. Parallel 
data transfers with external devices are made very easily through this parallel port. SP1 and SP2 are 
bi-directional serial ports. CNT1 and CNT2 are bi-directional synchronizing clock signals for each serial 
port. 



THE CONTROL PORTS 



PIN CONFIGURATIONS 



Control Port 1 



Control Port 2 



1 




2 




3 




4 




5 


o 


o 

6 


O 


O 

7 


O 


O 
8 


O 


O 
9 


O 

J 



Pin 


Type 


Note 


1 


JOYAO 




2 


J0YA1 




3 


J0YA2 




4 


J0YA3 




5 


POT AY 




6 


BUTTON A/LP 




7 


+ 5V 


MAX. 50mA 


8 


GND 




9 


POT AX 





Pin 


Type 


Note 


1 


JOYBO 




2 


J0YB1 




3 


J0YB2 




4 


J0YB3 




5 


POT BY 




6 


BUTTON B 




7 


+ 5V 


MAX. 50mA 


8 


GND 




9 


POT BX 





There are two Control ports, numbered 1 and 2. Each Controller port can accept a joystick or game 
controller paddle. A light pen can be plugged only into port 1 , CN3. The control port signals are tied 
to keyboard inputs and handled by the 6526 CIA device at U1. 



50 



THE KEYBOARD 



The CI 28 keyboard is an advance over the standard C64 keyboard. In 64 mode, only the standard 
66 keys are accessible. 

In 1 28 mode, 24 extra keys are available. They are the separate CURSOR keys, the HELP key, addi- 
tional FUNCTION keys, an ALPHA-LOCK key, the 40/80 key and a NUMERIC KEYPAD. These addi- 
tional keys are strobed by the VIC chip or are tied to dedicated 8502 or MMU I/O lines. 



Keyboard operations are controlled by the 6526 I/O device at location U1. 

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SCROLL 





KEY 



SHIFT 
LOCK 



SW 



RESTORE 






40/80 
DISPLAY 



SW 




CAPS 
LOCK 



SW 



KEYBOARD MATRIX 



51 



THE EXPANSION BUS 



The expansion bus available at CN 1 , is a parallel port that is used to connect program or game cart- 
ridges as well as special interfaces. 



PIN CONFIGURATION* 



22 21 20 1918 17 1615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 




ZY XWVUTSRPNMLKJHFEOCBA 



*See Sheet 1 of Schematic for line definitions. 



The CI 28 Expansion Bus is compatible with the C64 Expansion Bus, while at the same time allow- 
ing extended capabilities in C128 mode. 



CARTRIDGE ADDITION 



The CI 28 can use larger and more sophisticated cartridges than the C64 can. One of the main reasons 
for this is the new banking s che me use d in the CI 28 for external cartridges. The C64 uses two hard- 
ware control lines, EXROM and GAME, to control banking out of internal facilities and banking in of 
cartridge facilities. The CI 28 uses a software polling method, where, upon power-up, it polls the cart- 
ridge, according to a defined protocol, to determine if such a cartridge exists, and if so, its software 
priority. Since the CI 28 is always free to bank between cartridges and built-in ROM, an external ap- 
plication can take advantage of internal routines and naturally become an extended part of the CI 28, 
as opposed to becoming a replacement application. 



The elimination of EXROM and GAME as hardware control lines for cartridge identification, in CI 28 
mode, has freed up both of these lines for extended functioning. Both of the lines appear as bits in 
the MMU mode configuration register, and are both input and output ports. Neither has a dedicated 
function other than general cartridge function expansion and lend themselves to act as latched bank- 
ing lines or input sense lines. 



DMA Capability 

The CI 28 expansion bus supports DMAs in a fashion similar to that of the C64. A C64 DMA is 
achieved by pulling the DMA pin on the expansion bus low. Immediately after this happens, the RDY 
and AEC lines of the processor are brought low. This can cause problems, depending on what the 
processor is doing at the time. The RDY input of a 65xx series processor, when brought low, will 
halt the processor on the next 0i cycle, leaving the processor's address lines reflecting the current 
address being fetched. However, if the processor is in a w rite cy cle when RDY is brought low, it will 
ignore RDY until the next read cycle. Thus, in the C64, a DMA input occuring during a write cycle 
will tri-state the processor's address and data bus, but not stop it until up to three cycles later when 
the next read cycle occurs. The write cycles following th e DMA input do not actuall y writ e, causing 
memory corruption and often processor fatality when the DMA line is released. Any DMA input dur- 
ing (t>2 is a potentially fatal DMA. 



52 



THE EXPANSION BUS (Continued) 



If a proper DMA is asserted, the C64 tri-states and shuts down, allowing the DMA source complete 
access to the processor bus. Such a DMA source must monitor the </>2 arid BA outputs, as it must 
tri-state when the VIC is on the bus, and it must completely DMA when a VIC DMA is called for. 
The VIC chip always has the highest DMA priority. When on the bus, the DMA source has access 
to RAM, ROM, and I/O in the C64 DMA scheme. A proper DMA shutdown is usually achieved via 
some C64 software handshaking with the DMA source. 



The CI 28 mode uses a similar DMA sche me. When t he DMA input goes low, the RDY input to 
the 8502, the AEC input to the 8502, and the BUSRQST input to the Z-80, immediately go low. Ad- 
ditionally, the gated AEC signal, GAEC, goes low, causing the MMU to go immediately to its VIC cy- 
cle mode, and the Z-80 data-out buffer to tri-state. The DMA causes the Address to Shared Address 
buffer to reverse direction, and the Translated Address to Address buffer to be enabled, giving the 
external DMA source complete access to the processor Address Bus. The PLA is still looking at ungated 
AEC and, as such, will allow access to I/O devices, RAM, and ROM. There can be no access to the 
MMU. Thus, for CI 28 memory mapping, the memory map must be set up before being DM Aed. For 
C64 mode, memory mapping is done by the 8502 processor port lines and by the external EXROM 
and GA ME. Since the 8502 p orts will be inaccessible by a DMA source, only C64 map changes bas- 
ed upon EXROM and GAME can be made during a DMA. This is the same as is true in a C64 unit. 
All DMA sources, as with the C64, must yield to the VIC during <l>o or BA low. In order to use DMAs, 
the DMA source will most likely have to cooperate with a CI 28 mode program that allows the CI 28 
to shake hands in software with a DMA source to effect DMA non-destructively. A DMA source may 
also be able to monitor <t>o and R/W to achieve a non-destructive DMA, since unlike the C64, the CI 28 
does not tri-state the R/W line during VIC time. The R/W line will, of course, tri-state during a DMA 
to allow the DMA source to drive it, and care must be taken to look at the R/W line for this only after 
it becomes valid. In any case, <t>0 and BA must be constantly monitored to allow the VIC chip to function. 



53 



THE SERIAL BUS 



The CI 28 Serial Bus is an improved version of the C64/VIC 20 serial bus. The CI 28 improves this 
bus by allowing communication at much greater speeds with specially designed peripherals, the most 
important being the disk drive, while still maintaining capability with older, slower peripherals used 
by the VIC 20 and the C64. 



Serial Interface Connector 




Pin No. 


Signal 


Description 


1 


SERIAL SRO 


The slow serial bus does not use the SERVICE REQUEST line. 
The fast serial bus uses it as a fast bidirectional clock tine. 


2 


GND 


Chassis ground. 


3 


SERIAL ATN 


The ATTENTION line is a low active handshake used to 
address a device on the bus. 


4 


SERIAL CLK 


This is the slow serial CLOCK. It is used by slow serial devices 
to clock data transmitted on the serial bus. 


5 


SERIAL 
DATA 


The bidirectional serial DATA line is used by both slow and 
fast devices to transmit data in sync with a clock signal. 


6 


RES 


The RESET line is used to reset all peripherals when the host 
resets. 



I*— BVrC 5tNr UNDER ATTENTION (TD DLVICES ) 



ATN 



CAOCK 



DATA 




Lnjirmj^Rjui 



L DATA VALID 
LISTEMEW READV-FOR-t»TA 



*| |« — NORMAL DATA BVTti 



r 



rTALKEfl READY- TO-SEWD 
I rTAUER SENDING 



uumjumnn 



imiuwmu i 



L LISTTNER 
DATA-ACCEPTLO 



L 



TCWTA VALID 



lISIiNER RtADV- FOR-DA™ 



UUUUl 



LuSTENER DATA- ACCEPT to 



ATN 



END-OB-fOENTIFY HANDSHAKE (LAST BYTE JN MCSSAGE) 



CLOf 

Eata 



-.JUUUl 



^TALKER ftCADV-TO-StnO 

1 r-TALKER SENDING 



emuM 



Lfinjumnjin 



L 



n 



1 1 i 

I L II5TENER BEADY- FOR- DATA 

^ £01 -TINIEODT mnOSKF^KE 

IfSltNER READY- FDR- DATA 

SYSTEM LINE RELEASE-' 



TALK-ATTtNTlON TURNAROUND (TALKER!>U5Te-NeR TO LIST£NtR<= TALKER) 



ATN 



J 



CLOC 
DATA 



-.jmiu] 



iga 



r DEVICE ACRN0WLE6E5 IT 13 NOW TALKER 
I r TALKER REA0Y-TO-3EN 



uumrLJumn 



tu^^^miijyj L 



READ* FOR DATA 
BECOMES LISTENER CLDCR^ HI6H.DATA LOW 



Bus Operations 

There are three basic bus operations that take place on the serial bus, in both fast and slow modes. 
The first of these is called Control. The CI 28 is the controller in most circumstances. The controller 
of the bus is always the device that initiates protocol on the bus, requesting peripheral devices to 
do one of the two other serial operations, either Talk or Listen. 

All serial bus devices can listen. A Listener is a device that has been ordered by the Controller to 
receive data. Some devices, such as disk drives, can talk. A Talker can send data to the Controller. 
Both hardware and software drive this bus protocol. 



54 



THE SERIAL BUS (Continued) 



The Standard (Slow) Serial Bus 



The slow serial bus uses the port lines of the 6526 at U4, CIA 2, to drive ATN, CLK and DATA. 
The operation is the same as that of the C64 and when in C64 mode, slow to fast interference is 
automatically removed. 



The Fast Serial Bus 



In order to talk as a fast talker, the Controller must be addressing a fast device. When addressing 
any device, the CI 28 sends a fast byte, toggling the SRQ line eight times, with the ATN line low. 
If the device is a fast device, it will record the fact that a fast Controller accessed it and respond 
with a fast acknowledge. If the device is a slow device, no response is delivered and the CI 28 then 
assumes it is talking with a slow device. The status of the fast or slow is retained until the device 
is requested to untalk, unlisten, or if an error or system reset occurs. 

The fast serial bus, in order to achieve its speed increase, uses different hardware than that of the 
slow serial bus. The fast serial method is to use the serial port lines of the 6526 U1 , CIA 1 , pin 39, 
to actually transfer the serial data. This increases the transfer rate dramatically. 



The FSDIR bidirectional control line signals the MMU at U7, pin 44, that a fast device is present. 
The MMU then outputs control signals to the data direction buffer hardware for fast serial operation. 



55 



COMMON LINE DEFINITIONS 



AO A7 


PROCESSOR ADDRESS BUS 


LCR 


LOAD CONFIGURATION REGISTER 


AEC 


ADDRESS ENABLE CONTROL 


LP 


LIGHT PEN INPUT 


ATN 


ATTENTION LINE 


4 








MAO-MA 11 


MULTIPLEXED ADDRESS BUS 


BA 


BUS AVAILABLE 


MMU 


MEMORY MANAGEMENT UNIT 






MS 0-4 


MEMORY STATUS, ALSO INDENTIFIED AS 


C1 28/64 


C128 OR C64 MODE 


1 

i 


ROMBANK 


CAPLK 


CAPITAL LOCK 


MUX 


ADDRESS MULTIPLEX CONTROL 


CAS 


DRAM COLUMN ADDRESS STROBE 




MEMORY MULTIPLEX 


CASENB 


RAM COLUMN ADDRESS STROBE ENABLE 






CASS SENSE 


CASSETTE SENSE 


NMI 


NON-MASKABLE INTERRUPT 


CASS WRT 


CASSETTE WRITE 






CASS MTR 


CASSETTE MOTOR 


PHI 


2 MHZ CLOCK 


CHAROM 


CHARACTER ROM SELECT 


POT X,Y 


JOYSTICK PORT INPUTS 


CIA 


COMPLEX INTERFACE ADAPTOR 






CLR BNK 


COLOR RAM BANK SELECT 


RCR 


RAM CONFIGURATION REGISTER 


CNT 


COUNT INPUT 


RESET 


SYSTEM RESET 


COLORAM 


COLOR RAM CHIP SELECT 


ROM 1-4 


ROM CHIP SELECTS FOR OPERATING 
SYSTEM 


D0-D7 


DATA BUS 


ROM H,L 


CHIP SELECTS FOR EXPANSION ROMS 


DA0-DA7 


DISPLAY ADDRESS 


ROMBANK 




DD0-DD7 


DISPLAY DATA BUS 


0,1 


MEMORY STATUS SELECT 


DMA 


DIRECT IVIEMORY ACCESS 


RS 


REGISTER SELECT 


DOT CLK 


8.18 MHZ VIDEO DOT CLOCK 


RSTR 


RESTORE 


DRAM 


DYNAMIC RAM 


R/W 


READ/WRITE LINE 


DRESET 


DYNAMIC RAM RESET 






DWE 


DRAM WRITE ENABLE 


SA0-SA7 


SHARED ADDRESS BUS 


EXROM 


EXTERNAL ROM ENABLE 


TA8-TA15 


TRANSLATED ADDRESS BUS 


EXTRES 


EXTERNAL RESET 


TOD 


TIME OF DAY 






VA 14,15 


VIC ADDRESSES 


FROM 


FUNCTION ROM 


VIC 


VERSATILE INTERFACE CHIP 


FSDIR 


FAST SERIAL DIRECTION 


VMA0-VMA7 


VIC MULTIPLEXED ADDRESS BUS 


GAME 


GAME ROM ENABLE 


Z80EN 


Z-80 ENABLE 


GWE 


COLOR RAM WRITE ENABLE 


Z80 PHI 


Z 80 CLOCK 






ZD0ZD7 


Z-80 DATA BUS 


I/O 


I/O SELECT 






lOACC 


I/O ACCESS 


1 MHZ 


MASTER CLOCK IN 


IRQ 


INTERRUPT REQUEST 


40/80 SENSE 


40/80 COLUMN STATUS SENSE 



56 



COMMON I.C/S 
PIN ASSIGNMENTS AND LOGIC 



4066 

QUAD BILATERAL SWITCH 



PIN ASSIGNMENTS 



INTERNAL DIAGRAM 
(EACH SWITCH) 



DUAL-IN-LINE PACKAGE 



IN/OUT 



IN/OUT 
OUT/IN 

OUT/IN 

IN/OUT 

CONTROL B 

CONTROL C 

vss 




vdd 
control a 

control d 

IN/OUT 
OUT/IN 
OUT/IN 

IN/OUT 



CONTROL 






rVss 




II 



OUT/IN 



556 

DUAL TIMER 



PIN ASSIGNMENTS 



DISCHARGE 

THRESHOLD 

CONTROL 
VOLTAGE 

RESET 
OUTPUT 

TRIGGER 

GROUND 




CC 



DISCHARGE 



THRESHOLD 



DISCHARGE 


CONTROL VOLTAGE 


THRESHOLD 


RESET 


CONTROL 




VOLTAGE 




RESET 






OUTPUT 


OUTPUT 




TRIGGER 


TRIGGER 




GROUND 




FLIP FLOP 





FLIP FLOP 




DISCHARGE 



THRESHOLD 



CONTROL VOLTAGE 
RESET 



OUTPUT 



TRIGGER 



57 



COMMON I.C.'S (Continued) 



7400 • 74S00 • 74LS00 
QUAD 2-INPUT NAND GATE 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 



QNO 




i£]Vcc 







INPUTS 


OUTPUT 


A 


B 


Y 


L 
L 
H 
H 


L 
H 
L 
H 


H 
H 
H 
L 



H 
L 



HIGH voltage level 
LOW voltage level 



74LS03 

QUAD 2-INPUT NAND GATE (OPEN COLLECTOR) 



PIN ASSIGNMENT 



QND 




vcc 



LOGIC DIAGRAM 







TRUTH TABLE 



INPUTS 


OUTPUT 


A 


B 


Y 


L 
L 
H 
H 


L 
H 
L 
H 


H 
H 
H 
L 



H 
L 



HIGH voltage level 
LOW voltage level 



7406 

HEX INVERTER BUFFER/DRIVER (OPEN COLLECTOR) 



PIN ASSIGNMENT 



QND 




HI Vcc 



LOGIC DIAGRAM 








10 



TRUTH TABLE 



INPUT 


OUTPUT 


A 


Y 


H 
L 


L 
H 



H 
L 



HIGH voltage level 
LOW voltage level 




58 



COMMON I.C.'S (Continued) 



7407 

HEX BUFFER/DRIVER (OPEN COLLECTOR) 



PIN ASSIGNMENT 



OND 




iT] Vcc 



7408 • 74S08 • 74LS08 
QUAD 2-INPUT AND GATE 



LOGIC DIAGRAM 









TRUTH TABLE 



INPUT 


OUTPUT 


A 


Y 


H 
L 


H 
L 



H 
L 



HIGH voltage level 
LOW voltage level 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 



QND 




vcc 







INPUTS 


OUTPUT 


A 


B 


Y 


L 
L 
H 
H 


L 
H 
L 
H 


L 
L 
L 
H 



H 
L 



HIGH voltage level 
LOW voltage level 



7414 • 74LS14 

HEX INVERTER SCHMITT TRIGGER 



PIN ASSIGNMENT 



GND 




Vcc 



LOGIC DIAGRAM 









TRUTH TABLE 



INPUT 


OUTPUT 


A 


Y 



1 


1 




H 
L 



HIGH voltage level 
LOW voltage level 



59 



COMMON I.C.'S (Continued) 



7432 • 74S32 • 74LS32 • 74F32 
QUAD 2-INPUT OR GATE 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 



QNO 




vcc 






INPUTS 


OUTPUT 


A 


B 


Y 


L 
L 
H 
H 


L 
H 
L 
H 


L 
H 
H 
H 




H • HIGH voluga Iwel 
L > LOW voluga Uvtl 



11 



7474 • 74S74 • 74LS74 

DUAL D-TYPE FLIP FLOP (POSITIVE EDGE TRIGGERED) 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 




QNO 




OPERATING MODE 


INPUTS 


OUTPUTS 


§0 


Rd 


CP 


D 


Q 





Asynchronous Set 


L 


H 


X 


X 


H 


L 


Asynchronous Reset 


H 


L 


X 


X 


L 


H 


(Clear) 

Undetermined*** 


L 


L 


X 


X 


H 


H 


Load "1" (Set) 


H 


H 


I 


h 


H 


L 


Load "0" (Reset) 


H 


H 


1 


1 


L 


H 



H 

h 

L 

I 

X 

1 



HIGH voltage level steady state. 

HIGH voltage tevel one setup time prior to the LOWtoHIGH clock transition. 

LOW voltage level steady state. 

LOW voltage level one setup time prior to the LOWto-HIGH clock transition. 

Don't care. 

LOWto-HIGH clock transition. 



NOTE 

(a) Both outputs will be HIGH white both Sq and Rq are LOW. but the output states 
are unpredictable if Sq and Rq go HIGH simultaneously. 



74S138 • 74LS138 
DECODER/DEMULTIPLEXER 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 



lH Vcc 





INPUTS 


OUTPUTS 


ii 


e, 


Es 


Ao 


A, 


Aj 





T 


2 


3 


4 


5 


s 


f 

H 


H 


X 


X 


X 


X 


X 


H 


H 


H 


H 


H 


H 


H 


X 


H 


X 


X 


X 


X 


H 


H 


H 


H 


H 


H 


H 


H 


X 


X 


L 


X 


X 


X 


H 


H 


H 


H 


H 


H 


H 


H 


L 


L 


H 


L 


L 


L 


L 


H 


H 


H 


H 


H 


H 


H 


L 


L 


H 


H 


L 


L 


H 


L 


H 


H 


H 


H 


H 


H 


L 


L 


H ' 


L 


H 


L 


H 


H 


L 


H 

1 


H 


H 


H 


H 


L 


L ; 


H 


H 

1 


H 


L 


H 


H 


H 


L 


H 


H 

1 


H 


H 


L 


L ■ 


H 


1 

L 


L 


H 


H 


H 


H 


H 


L 


H 


H 


H 


L 


L 


H 


H 


L 


H 


H 


H 


H 


H 


H 


L 


H 


H 


L 


L 


H 


L 


H 


H 


H 


H 


H 


H 


H 


H 


L 


H 


L 


L 


H 


H 


H 


H 


H 


H 


H 


H 


H 


H 


H 


L 



NOTES 

H=HIGH voltage tevet 
L => LOW voltage level 
X M Don^t care 



60 



COMMON I.C.'S (Continued) 



74S244 • 74LS244 
OCTAL 3-STATE BUFFER 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 



GNO 



13 Vcc 
TEOEb 




17 



IS 



13 



11 



5E. 



19 



BE. 




INPUTS 


OUTPUT 


OEa 


la 


OEb 


■b 


Ya 


Yb 


L 

L 
H 


-1 I X 


L 
L 
H 


L 
H 
X 


L 

H 

(Z) 


L 
H 

(Z) 



H = HIGH voltage level 

L = LOW voltage level 

X = Don't care 

Z = HIGH impedance "off" state 



74LS245 • 74F245 
OCTAL BUS TRANSCEIVER 

PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 




GND 




INPUTS 


INPUTS/OUTPUTS 


OE 


S/R 


An 


Bn 


1 

L 
H 


- X X 


A = B 

INPUT 

(Z) 


INPUTS 
B = A 

(Z) 



H 
L 
X 



HIGH voltage level 
LOW voltage level 
Don't care 



(Z) = HIGH impedance "off" state 



72S257 • 74LS257 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 



I 



Oa 



1 



I 
I 



Ob 
1b 



GND 




oe 



'1 



•Ob 



'lb 



^ 



1c 



>0d 



'Id 



vcc 

OE 
lOd 



1d 



I 



Oc 



I 



1c 




V^c = Pin 16 
GNO = Pine 



ENABLE 


SELECT 
INPUT 




OE 


S 




H 
L 
L 
L 
L 


X 

H 
H 
L 
L 




INPUTS 


OUTPUT 




lo 


li 


Y 




X 
X 
X 

L 
H 


X 
L 
H 
X 
X 


(Z) 
L 
H 
L 
H 





H =HIGH voltage level 
L = LOW voltage level 
X = Doni care 
(Z) = HIGH rmpedance (off) state 



61 



COMMON I.C.'S (Continued) 



72S258 • 74LS258A 

QUAD 2:1 MULTIPLEXER (3-STATE) 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 





vcc -Pirn* 

QNO-Plfil 



74S373 • 74LS373 
OCTAL LATCH (3-STATE) 



OUTPUT 
ENABLE 


SELECT 
INPUT 


DATA 
INPUTS 


OUTPUTS 


SE 


S 


lo 


li 


Y 


H 

L 
L 

L 
L 


X 

H 
H 

L 
L 


X 
X 
X 

L 
H 


X 

L 
H 
X 
X 


(Z) 
H 

L 

H 

L 



H > HIGH voltags level 

L * LOW voltege level 

X « Don't care 

(Z) « HIGH impedance (off) state 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



6i 

ONO 




Vcc 

07 

D4 
Q4 




Vcc ■ Ptn 20 
QND-mniO 



(1) *^ 




Oo 



'1 



Oj Q3 Q4 



TRUTH TABLE 



05 



Oe 



07 



OPERATING MODES 


INPUTS 


INTERNAL REGISTER 


OUTPUTS 


61 


E 


Do 


Q0-Q7 


Enable and read register 


L 
L 


H 
H 


L 
H 


L 
H 


L 
H 


Latch and read register 


L 
L 


L 
L 


1 
h 


L 
H 


L 
H 


Latch register and disable outputs 


H 
H 


L 
L 


1 
h 


L 
H 


(2) 
(Z) 



H > HtGH voltage level 

h > HtGH voltage level one setup time prior to itM LOW-to-HIQH clock transition or 

HIGH-to-LOW 5? transition 
L - LOW voltage level 



I s LOW voltage level one setup time prior to irw LOW-to-HIGH clock transition or 

HIGH-to-LOW (5? transition 
(Z)> HtGH impedance "off" sUte 
t . LOWto-HIGH ckwk transition 



62 



25 2037-0 J 




note: : 

/\ LOW END ONLV 
/^HIGH E.ND OMLY 



BOARD LAYOUT 

PCB ASSY /^310379 Revision 6 

IDENTIFYING FACTOR: On solder side of board 

at the EXPANSION BUS, CN1, the artwork 

/^310381 REV. 6 appears. 



63 



PARTS LIST 
PCB ASSEMBLY #310379 

REV. 6 



INTEGRATED CIRCUITS 


DIODES (Continued) 


U1 


6526 CIA 


906108-01 


CR13 


Bridge Rect 100V 2A 251026-01 


U2 


4066 




CR15,16 


1N914 


U3 


74LS138 




CR100,101 


1N914 


U4 
U5 


6526 CIA 
6581 SID 


906108-01 
906112-01 










U6 


8502 Microprocessor 


315020-01 


RESISTORS - All values in ohms, 1/4W, 5% 


U7 
U8 


8722-R1 MMU 
74LS08 


310389-01 




unless noted otherwise. 


R1 
R2 


68 
100 


U9 


74LS32 




U10 


Z80B Microprocessor 6 MHz 


906150-02 


R3 


IK 


U11 


8721-R3 PLA 


315012-01 


1 1 ^^ 

R4 


1 1 X 

100 


U12 


74LS373 




1 l^T 

R5 


1 ^^ 

470 


U13 


74LS244 




V 1 %^ 

R6 


47K 


U14,15 


74LS257A 




R7 


560 


U16 


74LS14 




R8 


3.3K 


U17 


74ALS373 




R9 


10K 


U18 


ROM 64K 128 Char 


390059-01 


RIO 


3.3K 


U19 


2016 16K RAM - 200ns 




R11,12 


IK 


U20 


4066 




R13,14 


330 1W5% 


U21 


8564-R4 VIC 


315009-01 


R16 


120 


U22 


8563-R7 CRT Cntrl 


315014-01 


R17 


47 


U23 


4416 Dynamic RAM - 150ns 




R18 


82 


U24 


74LS244 




R19 


330 1W 5% 


U25 
U26 


4416 Dynamic RAM - 150ns 
74LS257A 




R20 
R21 

M^ ^^ ^% 


10K 
470K 


U27 
U28 


556 

8701 Clock Generator 


251527-01 


R22 
R23 
R24 


47K 

100K 

47K 


U29,30 


7406 




R25 


WW W ^ 

100K 


U31 


74LS00 




R26 


100 


U32 


ROM 1 - C64 Kern & Basic 


251913-01 


R27 


4.7K 


U33 


ROM 2 - Basic $4000 


318018-02 


R28 


V V H V ^m 

10K 


U34 


ROM 3 - Basic $8000 


318019-02 


R29,30 


68 


U35 


ROM 4 - Kernal $C000 


318020-03 


R31 


100 


U36 


ROM Mem Function 


Blank 


R32 


180 


U37 


7406 




R33,34 


10K 


U38-53 


4164 Dynamic RAM — 200ns 




R35 


100 


U54 


74LS32 




R36 


10K 


U55 


74LS245 




R38 


10K 


U56 


74LS74 




R39 


120 


U57 


7407 




R40 


180 


U58 


74LS03 




R41 


680 


U59 
U60 


7812 Regulator 12V, To-220 Case 
7407 


R42 

R43,44 

R45 


180 
3.3K 
1 2K 


U61 


74LS08 




W 1 ■ \^ 

R46 


3.3K 


U62 


74LS244 




R47 
R48 


IK 
10K 








TRANSISl 


ORS 




R100,101 


IK 








R102 


47K 


Q1,2 


2SC1815 




R1 03,04 


IK 


Q3 


2SD880 




R105 


470 


Q4,5,6 


2SC1815 




R106 


IK 


Q100 
Q101 


2N4403 
2SC1815 












Q102 


2N4403 




RESISTOR 


! PACKS 


DIODES 




RP1 
RP2 


IK +/-2% 8 Pin, SIP, Pin 1 Com 
IK 1/8W +/-10% 9 Pin, SIP, Pin 1 Com 








CRl 


RD6.8EB Zener 6.8V 400MW I 


RP3,4 


33 +1-2% 8 Pin, SIP, Isolated 


CR2-7 


1N914 


Sub: IN4148 


RP5 


3.3K +/-10% 8 Pin, SIP, Pin 1 Com 


CR8 


1N4371 Zener 2.7V 500MW 


RP6 


IK 1/8W +/-10% 9 Pin, SIP, Pin 1 Com 


CR9 


1N914 


Sub: IN4148 


RP7,8 


3.3K 10 Pin, SIP, Pin 1 Com 


CRIOJI 


1N4001 


Rect 50V 1 A 


RP9,10 


10K 10 Pin, SIP, Pin 1 Com 



64 



PART LIST PCB ASSEMBLY 310379 REV. 6 



CAPACITORS - All caps are 25v, +80%, 


CAPACITORS (Continued) 






-20% uniess noted otherwise. 








CI 


Cer 


• VF 




C105 


Elect 330/iF, 50V, 


+ /-20% 


C2 


Cer 


lOOOOpF 




C106 


Elect 1000/iF, 25V 




C3-5 


Cer 


.IF 




C107 


Elect 1 00/iF, 1 6V 




C6 


Cer 


.22/tF 




C108,9 


Cer 1800pF, 50V 


10% 


C7-19 


Cer 


.l/iF 




C110 


Cer 1 0OOOpF 




C20 


Trim 


4-40pF 




cm 


Elect Alum 10/iF, 16V 




C21 


Cer 


.22mF 




C112 


Cer 470pF, 50V. 


10% 


C22 


Cer 


■ VF 




C113,14 


Cer 1 0OOOpF 




C23 


Cer 


.22/tF 




C115,16 


Cer . 1 /iF 




C24 


Cer 


• VF 




C1 17-23 


Cer 1 0OOOpF 




C25 


Cer 


.22/iF 




CI 24 


Cer .1/iF, 16V 




C26,27 
C28 


Cer 
Cer 


.VF 
.22/iF 










MISCELLANEOUS 




C29-37 
C38-53 


Cer 
Cer 


• VF 
.22/iF 
















C54-58 


Cer 


• VF 




Y1 


16 MHz Clock Oscillator 


325566-01 


C60 


Cer 


■ VF 




Y2 


14.31818 Crystal 


251467-01 


C61-63 


Elect Alum 


10/tF, 16V 










C64,65 


Cer 


1 OOOOpF 




LI -4 


Inciuctor 2.2/iH 




C66 


Mylar 


.OVF, 250V, 


+ /-20% 


L5 


Line Filter Assy 


251878-01 


C67 


Cer 


1 0OOOfiF 










C68 


Cer 


■ VF 




FB1-15, 


Ferrite Beads 




C69 


Elect Alum 


10/iF, 16V 




18-20 






C70,71 


Cer 


■ VF 










C72,73 


Cer 


470pF, 50V, 


10% 


EMM, 2 


EMI Filter 


47pF 


C74 


Cer 


1 OOOOpF 




EMt3-6 


EMI Filter 


lOOpF 


C75 


Cer 


470pF, 50V, 


10% 


EMI9-11 


EMI Filter 


47pF 


C76 


Cer 


• * 

.1/iF 




EMU 2-35, 


EMI Filter 


lOOpF 


C77 


Cer 


1 OOOOpF 




37.38 






C78,C79 


Cer 


lOOOpF, 50V, 


10% 


EMI39 


EMI Filter 


270pF 


C80 


Elect 


2.2/iF, 25V 




EMI40-42 


EMI Filter 


lOOpF 


C81 


Cer 


lOOOpF, 50V, 


10% 


EMI44-50 


Ferrite Bead 




C82,83 


Cer 


470pF, 50V, 


10% 


EMI69 


EMI Filter 


lOOpF 


C84 


Cer 


220pF, 50V, 


10% 








C85 


Elect Alum 


lO/tF, 16V 




Ml 


Modulator 


251917-01 


C86 


Cer 


• VF 










C87 


Cer 


.22,iF 




SW1 


Rocker Switch 


252182-01 


C88 


Elect Alum 


10/iF, 16V 




SW2 


Push BT SPOT 


251260-01 


C89 


Cer 


51 pF, 50 V, 


+ /-5% 








C90 


Cer 


360pF, 50V, 


+ /-5% 


CN1 


RT Angle Card Edge 


906100-02 


C91 


Elect 


VF, 16V 




CN3,4 


Mini D Cnnct Joyl,2 


251057-01 


C92 


Elect Alum 


1 0/tF, 1 6V 




CN6,7 


6 Pin Din Serial Cnnct Shid 


252166-01 


C93 


Cer 


• VF 




CN8 


8 Pin Din Video Cnnct ShId 


252168-01 


C94 


Cer 


.22/tF 




CN10 


D Cnnct 9 Pin Fem Rgbi 


252024-01 


C95 


Cer Mono 


.22/iF, 100V, 


+ 80%, -20% 


CN11 


5 Pin Square Din Shielded 


252167-01 


C98-99 


Cer 


.22mF, 50V 




CN13 


3 Pin Header .1 Center 




CI 00 


Cer 


.1/iF 






Shield Box 


326265-02 


C101 


Elect 


10/tF, 35V, 


+ /-20% 




Shield Cap 


310407-01 


C102 


Cer 


.1/iF 










C103 


Cer 


1 OOOOpF 










C104 


Elect 


220/iF, 50V 











65 



D 



QUICK REFERENCE 



TITLE 


PAGE 


4066 


57 


6526 


49 


74XXX 


58 


BUS ARCHITECTURE 


4 


CASSETTE PORT 


49 


CONTROL PORTS 


50 


EXPANSION BUS 


52 


KEYBOARD 




Test 


51 


Matrix 


51 


LINE DEFINITIONS 


56 


SERIAL BUS 


54 


USER PORT 


50 



c 



B 



A 



8 



6 



5 




4 



3 



-f5V 



D 



S 

CI - 




.+ 5V 



0- 

s 



c 



u 



Ufy 




V 

c 

I 

2 
3 

4 

a 



9 47PF 

— S 



n ^trr 




c 




CKPLK SENSE 

SQ£E. 



I PQTAr n 



4 




14 



Ll2 





POTA 




1 




R32 



B 



SCIUKL BUS 

4 Pin otN 

conncctoa 


1 

5 

4 
» 

2 






^'^H 




QUO 



A 



INTERNAL 
SERIAL BUS 

TPlMPoar 
CONlieCTOR 



'> 4^ 







♦ 5V 



74^06 



7406 



*P&-<<5^ 




20 



DATA XJT 7 «fc5 

PA4 J 

PAS N 

PAU "Q 

PAT -• 




CLKIN 3 



DATA IN 9 



SV 




CM 




3JIIH9M 

cut 

USER PORT 

£e4ft4AL£rD«C) 



CIAI 

CASS SCNSC / P4 

CAJSWRT /P3 

CASSMKT/P5 

128/44 




lb 



17 



CMT CVJ 




liilU. 



14 P»4 
T?|PB5 

P&4» 
PB7 



4-5V 




♦5V 




TOO 





vsn* 




25 





9MCI 




R46 
3.3K 



iSS 



4SV 



n 




+5V 



2 



1 




B 



POTX 
POJY 
LP 



4«/» 5£NSE 

0»-D7 



D 
I 

Z 
3 

4 

5 
6 

7 

6 

9 

10 
II 

(2 
13 



^m 




B 



CNI 

exfHNolONBJS 

44 PIN 
F£MAlC edge 





R4 3 
3.3 K 



+5V 



W^o<<RP5-7 
3.3KSS 3.3K 




C»TC, DCK 



GAMC 



DMA 



>n(/i m 






ROMH 



I MHZ 



■ I > TAfl-T4l5 




;»SAi?-S47 






2.7V ZCNCR 
CR8 




CIA2 



REV k BD 




1/0 CONMecTQR 



7407 



/^ LOW END ONLV 
A Hl(^ CND ONL>r 



8 



7 



6 



5 



t 



I/O 



Control Ports, Keyboard, 



User Port, Serial Port, Cassette Port 
SCHEMATIC 310378 REV. 6 



Sheet 1 of 4 



4 



3 



2 



1 



D 



C 




B 



A 



66 



QUICK REFERENCE 



TITLE 


PAGE 


6581 


38 


74XXX 


58 


8502 


6 


8721 


29 


8722 


27 


BUS ARCHITECTURE 


4 


LINE DEFINITIONS 


56 


MEMORY ARCHITECTURE 


11 


MMU 




Text 


20 


Pin Configuration 


27 


PLA 




Text 


28 


Pin Configuration 


29 


SID 


38 


Z80 




Text 


8 


Pin Configuration 


10 



( 



E 



^ 



8 



7 



6 



5 




4 



3 



2 



1 



D 



C 



B 



A 



09 'Dl 

AB-Aff 



+ I2V 



C8fr .Uf 



rXT AUDIO 
POTX 
POTt 



CASS IMTR/PSI 

CASS SENSE/ P4{ 

CASS WR1 / P3 





AUDIO OUT 

DA -07 
AO- AI5 

SA^-SA.7 



VMi^ 



MAft - MAT 



-7A»5/ 
- MAI I 




D 



C 




■Z80 PHI 



B 



cBCwro 



A 



ICROPROCESSORS, MMU, SID, 

PLA, POWER SUPPLY 
SCHEMATIC 310378 REV. 

Sheet 2 of 4 



8 



6 



5 




3 



2 



1 



67 



QUICK REFERENCE 



TITLE 


PAGE 


2016 


17 


4066 


57 


4416 


19 


556 


57 


74XXX 


58 


8563 


38 


8564 


35 


8701 


30 


BUS ARCHITECTURE 


4 


CLOCK 


30 


LINE DEFINITIONS 


56 


MEMORY ARCHITECTURE 


11 


MODULATOR 


77 


RAM 


17 


ROM 


15 


VIC 




Text 


33 


Pin Configuration 


35 


VIDEO CONTROLLER 




Text 


36 


Pin Configuration 


38 


VIDEO INTERFACE 

1 

1 
1 


33 



8 



7 



6 



5 




4 



3 



2 



1 



Audio 






TA0-TAII 

ClASnk 



D 



i0A7 




DMA 



128/64 
CAPSUK 



C 



TOR 
VMA# -VMA7 




B 



117, joui-r 



LZ ZJm** 



U28 




H.3tAlB MHi -MTSC 

a 17.73447 MHi PAL 
CL ' Idpf 



DOT CLOCK 



2S0PHI 



A 




CMS 



g 



2 

D-2 



00 



o 



£XT AUDlfi 



^SHOULD BC USXD OA^ 
PROPOCriOKJ ^QB 



cNie 



RSTR 



8 



7 



6 



5 



t 



BVSREQ 



VIDEO, CLOCK, RESET 
SCHEMATIC 310378 REV. 6 

Sheet 3 of 4 



3 



2 



1 



D 



C 




B 



3 
4 


Sa 


1 
5 


22 




au 


C» 


«- ^ 




0^2 


7 


2 




;;; O 


3 : 


CO CJ 




o 


9 


QC 


/ 

1 




2 ! 





A 



68 



QUICK REFERENCE 



TITLE 


PAGE 


23128 


16 


4164 


18 


74XXX 


58 


BUS ARCHITECTURE 


4 


LINE DEFINITIONS 


56 


MEMORY ARCHITECTURE 


11 


RAM 


17 


ROM 


15 



8 



7 



6 



5 




4 



3 



2 



1 



TAie 

128/64 



D 



CtX>SE -3SC.KRGM J Al 
TJkl4 



Ae-Al5 



c 




B 



-A8-TAIS ( 




D 



C 




B 



A8-AI5 



MAe - MAI 

Da- Di 



A 



A 



8 



7 



6 



5 




4 



3 



RAM, ROM 
SCHEMATIC 310378 REV. 6 

Sheet 4 of 4 



69 



2 



1 



324,f fl-Ot 




903^i7-o^ 



NOTE ■■ 





LOW END ONLY 
H/GH END ONLY 



BOARD LAYOUT 

PCB ASSY #310379 Revision 7 

IDENTIFYING FACTOR: On solder side of board 

at the EXPANSION BUS, CN1, the artwork 

#310381 REV. 7 appears. 



70 



PARTS LIST 
PCB ASSEMBLY #310379 

REV. 7 



INTEGRATED CIRCUITS 


DIODES (Continued) 


U1 


6526 CIA 


906108-01 


CR13 


Bridge Rect 100V 2A 


251026-01 


U2 


4066 




CR15,16 


1N914 


Sub: IN4148 


U3 


^^^ ^^^ ^^^ 

74LS138 




CR100 


1N914 


Sub: IN4148 


U4 
U5 


6526 CIA 
6581 SID 


906108-01 
906112-01 














U6 


^^^ ^^^ ^^r ^^^ ■ ^^^ 
1 

8502 Microprocessor 


315020-01 


RESISTORS — All values in ohms 


, 1/4W, 


U7 
U8 


8722-R1 MMU 
74LS08 


310389-01 




5% unless noted otherwise. 


R1 


68 




U9 


74F32 




■ 11 

R2 


100 




U10 


Z80B Microprocessor 6 MHz 


906150-02 


R3 


IK 




U11 


8721-R3 PLA 


315012-01 


i 1 ^^ 

R4 


■ I « 

100 




U12 


74LS373 




1 l^T 

R5 


1 ^^^^ 

470 




U13 


74LS244 




R6 


47K 




U14,15 


74LS257A 




R7 


560 




U16 


74LS14 




R8 


3.3K 




U17 


74ALS373 




R9 


10K 




U18 


ROM 64K 128 Char 


390059-01 


RIO 


3.3K 




U19 


2016 16K RAM - 200ns 




R11,12 


IK 




U20 


4066 




R13,14 


330 1W 5% 




U21 


8564-R4 VIC 


315009-01 


R16 


120 




U22 


8563-R7 CRT Cntrl 


315014-01 


R17 


47 




U23 


4416 Dynamic RAM — 150ns 




R18 


82 

^^L ^i^ ^^b ^ L A ■ ^^b J^ J 




U24 


74LS244 




R19 


330 1W 5% 




U25 
U26 


4416 Dynamic RAM - 150ns 
74LS257A 




R20 
R21 
R22 


10K 

470K 

47K 




U27 
U28 


556 

8701 C Clock Generator 


251527-03 


R23 
R24 


100K 
47K 




U29,30 


7406 




■ 1 ^ r 

R25 


100K 




U31 


74LS00 




R26 


100 




U32 


ROM 1 - C64 Kern & Basic 


251913-01 


R27 


4.7K 




U33 


ROM 2 - Basic $4000 


318018-02 


R28 


10K 




U34 


ROM 3 - Basic $8000 


318019-02 


R29,30 


68 




U35 


ROM 4 - Kernal $C000 


318020-03 


R31 


100 




U36 


ROM Mem Function 


Blank 


R32 


180 




U37 


7406 




R33,34 


10K 




U38-53 


4164 Dynamic RAM - 150ns 




R35 


100 




U54 


74LS32 




R36 


lOK 




U55 


74F245 




R38 


10K 




U56 


74LS74 




R39 


120 




U57 


7407 




R40 


180 




U58 


74LS03 




R41 


680 




U59 
U60 


7812 Regulator 12V, TO-220 CASE 
7407 


R42 

R43,44 

R45 


180 

3.3K 

1.2K 




U61 


74LS08 




R46 


3.3K 




U62 


74LS244 




R47 


IK 




U63 


7406 




R48 

RIOOJOI 

R102 

1 
1 

1 


10K 
1K 




TRANSISTORS 


1 IX 

68 




Q1,2 


2SC1815 










Q3 


2SD880 




RESISTOR 


t PACKS 




Q4,5,6 


2SC1815 










^^^ 1 ^ 1 V 




RP1 


IK +/ 2% 


8 Pin SIP Pin 1 Com 


DIODES 


111 1 

RP2 

RP3,4 

RP5 


1 IX if ^ /u 

IK 1/8W +/-10% 
33 +/-2% 
3.3K +/-10% 


u r II If wir / rill i wUi 1 1 

9 Pin, SIP, Pin 1 Com 
8 Pin, SIP, Isolated 
8 Pin, SIP, Pin 1 Com 


CR1 


RD6.8EB Zener 6.8V 400MW 


CR2-7 


1N914 ■ 


Sub: IN4148 


RP6 


IK 1/8W +/-10% 


9 Pin, SIP, Pin 1 Com 


CR8 


1N4371 Zener 2.7V 500MW | 


RP7,8 


3.3K 


10 Pin, SIP, Pin 1 Com 


CR9 


1N914 


Sub: IN4148 


RP9,10 


10K 


10 Pin, SIP, Pin 1 Com 


CR10,11 


1N4001 


Rect 50V 1 A 









71 



PART LIST PCB ASSEMBLY 310379 REV. 7 



CAPACITORS - All caps are 25v 


. +80%. 


CAPACITORS (Continued) 






-20% unless noted otherwise. 








CI 


Cer 


• VF 






C105 


Elect 330/xF. 50V, 


+ /-20% 


C2 


Cer 


.01/xF 






C106 


Elect lOOO/iF, 25V 




C3-5 


Cer 


.IF 






C107 


Elect 100/iF, 16V 




C6 


Cer 


.22/iF 






C108,9 


Cer .01 /iF 




C7-19 


Cer 


■ VF 






Clio 


Cer .01 /iF 




C20 


Trim 


4-40pF 






cm 


Elect Alum 10/iF, 16V 




C21 ! 


Cer 


.22/iF 






C112 


Cer 470pF, 50V, 


10% 


C22 


Cer 


.l/xF 






C113.14 


Cer .OVF 




C23 


Cer 


.22mF 






C115,16 \ 


Cer .VF 




C24 


Cer 


• VF 






C1 17-23 


Cer .OVF 




C25 


Cer 


.22mF 






CI 24 


Cer .VF, 16V 




C26,27 


Cer 


• VF 






C125,126 


Cer .OVF 




C28 
C29-37 

_. 1 


Cer 

Cer 


.22/iF 
■ VF 












MISCELLANEOUS 




C38-53 
C54-58 


Cer 
Cer 


.22/tF 
-VF 


















C50 


Cer 


-VF 






Y1 


16 MHz Clock Oscillator 


325566-01 


C61-62 


Elect Alum 


lO^F, 


16V 




Y2 


14.31818 Crystal 


251467-01 


C63 


Elect Alum 


1 0OfiF, 


6.3V 










C64,65 


Cer 


.OVF 






LI -4 


Inductor 2.2/tH 




C66 


Cer 


.OVF, 


25V 


A 


L5 


Line Filter Assy 


251878-01 


C67 


Cer 


.01 /iF 












C68 


Cer 


• VF 






FB1-15, 


Ferrite Beads 




C70,71 


Cer 


• VF 






18-20 






C72,73 


Cer 


470pF, 


50V, 


10% 








C74 


Cer 


.OVF 






EMU, 2 


EMI Filter 


47pF 


C75 


Cer 


470pF, 


50V, 


10% 


EMI3-6 


EMI Filter 


lOOpF 


C76 


Cer 


.l/iF 






EMI9-11 


EMI Filter 


47pF 


C77 


Cer 


.OI/iF 






EMU 2-35, 


EMI Filter 


lOOpF 


C78,C79 


Cer 


1 0OOpF, 


50 V, 


10% 


37,38 






C80 


Elect 


2.2mF, 


25V 




EMI39 


EMI Filter 


270pF 


C81 


Cer 


lOOOpF, 


50V. 


10% 


EMI40-42 


EMI Filter 


lOOpF 


C82,83 


Cer 


470pF, 


50 V, 


10% 


EMI44-50 


Ferrite Bead 




C84 


Cer 


220pF. 


50 V, 


10% 


EMI69 


EMI Filter 


lOOpF 


C85 


Elect Alum 


lO^F, 


16V 




Ml 


Modulator 


251917-01 


C86 


Cer 


-VF 












C87 


Cer 


.22mF 






SW1 


Rocker Switch 


252182-01 


C88 


Elect Alum 


10/iF, 


16V 




SW2 


Push BT SPOT 


251260-01 


C89 


Cer 


51pF, 


50V. 


+ /-5% 




1 




C90 


Cer 


360pF, 


50V. 


+ /-5% 


CN1 


RT Angle Card Edge 


906100-02 


C91 


Elect 


VF. 


50V 




CN3,4 


Mini D Cnnct Joy1,2 


251057-01 


C92 


Elect Alum 


lO/iF, 


16V 




CN5 


Keybd Cnnct 


252062-01 


C93 


Cer 


-l/tF 






CN6 


6 Pin Din Serial Cnnct Shid 


252166-01 


C94 


Cer 


.22/iF 






CN8 


8 Pin Din Video Cnnct ShId 


252168-01 


C95 


Cer Mono 


.22mF. 


100V, 


+ 80%. -20% 


CN10 


D Cnnct 9 Pin Fem Rgbi 


252024-01 


C96-99 


Cer 


■ VF, 


16V 




CN11 


5 Pin Square Din Shielded 


252167-01 


C100 


Cer 


• VF 






CN13 


3 Pin Header .1 Center 




C101 


Elect 


10/xF, 


35V, 


+ /-20% 




Shield Box 


326265-02 


C102 


Cer 


•VF 








Shield Cap 


310407-01 


C103 


Cer 


.OVF 












C104 


Elect 


220tiF, 


50V 











72 



% 



[ 



QUICK REFERENCE 



TITLE 


PAGE 


4066 


57 


6526 


49 


74XXX 


58 


BUS ARCHITECTURE 


4 


CASSETTE PORT 


49 


CONTROL PORTS 


50 


EXPANSION BUS 


52 


KEYBOARD 




Test 


51 


Matrix 


51 


LINE DEFINITIONS 


56 


SERIAL BUS 


54 


USER PORT 


50 



c 



E 



; 



8 



7 



6 



5 



; 



4 



3 



2 



1 



D 







0" 






00 






o 




o 


w 




2 


< 


z 


S 


u 


a 


(\j 



POTX 

POTY 
LP 



4A/W5CNSE 

D»-D7 



c 



DOT CLOCK 




B 



A 




C 




>Da>-D7 



> I MHZ 



B 



>TAa-TAI5 



SERIAL BUS 

6 Pin CMn 

connector 



0-SA7 



> VA 14 



I/O CONMECTOR 



7PIM POST 

CON M ECTOR 
CN7 



IGH tJslD ONLX 



Control Ports, Keyboard, 
User Port, Serial Port, Cassette Port 
SCHEMATIC 310378 REV. 7 



Sheet 1 of 4 



8 



7 



6 



5 



t 



4 



3 



2 



1 



73 



QUICK REFERENCE 



TITLE 


PAGE 


6581 


38 


74XXX 


58 


8502 


6 


8721 


29 


8722 


27 


BUS ARCHITECTURE 


4 


LINE DEFINITIONS 


56 


MEMORY ARCHITECTURE 


11 


MMU 




Text 


20 


Pin Configuration 


27 


PLA 




Text 


28 


Pin Configuration 


29 


SID 


38 


Z80 




Text 


8 


Pin Configuration 


10 



8 



6 



3 



2 



1 



D 



C 



B 



D»-D7 I 
Aa- Al5 




(XJ AUDIO 

POIX 
POTY 




Cltt*^ J- Clffife 




CAPLK SENSE I > 



Rfc 
47 K 





tl2 
Z5Ct8l5 






:: 



CB4 



IRD 



NWI 

CASS MTR/PSl 
CASS SENSE/P4 
CASS WRT/P3 

2MH£ I 
P(MH? 




B 




DMA 




BA [ 



NOTE : 

/l\ LOW END ONLY 
/^ HIGH ENO OMLV 

if 

.v.^.o-l 111 l-o 



CBiiZ 
IN40(2I 




+/;>/ 



CNI I 

CNI2 

^^ 

0)d 



^JTTT 



C^5 



loo Vj 
T VAC IN 



4 
2 



45IN 



Sit 





Cl(t4 , 



CRll UNPEG. 
IMflffll *sv 









uJ 
O 

a 



u 



CL _ 

^8 



6 

5 
4 
3 

2 



SHIELD ^)l^ 
/6\ 



SVACIM 



qVA21N 



■•E \' 



5I&&WD 



SHIELD 




LOGIC 
GROUND 



ClOfc 

lOOQii 
25V 



l^f ' 

cie? 




<fVAC2 
SVACl 




*5V 




1/02 
I/O I 



rnrr 

CS55C3 
e xRQM 
GAME 
40/BC 
VAI4 



8 




3^ 



w 



MC 



12 

13 






< Y7 

Y5 

Y4 

y - 



C 
B 
A 



U3 



(^3 



14LS138 
3 Al I 



i 



Al 



I 



A& 



J 



*^/ 



5 TDT^ 



74LS0D 




16 



21 



2MHZ I 



RES 
IRO 



R/VV 



WM2 

PS 
P4 

P3 




'JC 






P2, 3g ^tf^>3AY 



7407 



Z 




=: 




s^Ai 



^A2 



zo 



vAi 



|9 



Ae 1 6 

D7 4 2 



VDG> 4 I 



kD4 



D5 £0 



39 



kD3 38 

D2 



37 



DI 



3(£. 



DO 35 



4<^ 



il 



AVA4 

A3 
A2 
Al 

A0 

D7 
DC 
DS 
D4 
D3 
02 
DI 

7 



MUX 
R/W 

AEC 
87 22 

MMU 

\n 

esSTn 

TAIS 

TAI4 

TAI3 

7AI2 

TAIl 

TAia 

TAS 

TAB 



17 Muy. 



ii 



l(i) 






4-5V 





PP7-8 



TiivT^ff 



i^rf'i 



MS3 
MSZ 
■MSI 
MSB 



H8?EN 



^ 



R34 I0K 




♦ Sv 





BUSRQ 



ffb 



21 



PHI tKi 



:1|^ 




JMA 



7M3/ 



8 



10 



TAl2. 

7AI L m;^ii 



7AI0. h/fA.lO 
TA?. MA9 
J^fi/" MAS 



47 128/fc4 



(3 I/0 5tL 



IS rombam*;ld 



48 



^ M 

GAME 
4(£)/80 




F5DIR 



14 ROMBANKHI 



BM 



/ 




R/ 



AEC 



LORAM 22 



HIRAM 



AREN 25 



^HIR 



BUSACK 13 



L 



CLOSED 

EMABLC 
CAS LATCH 



)Z 



II 



FSDIR 



opew- 

1?&)CR0M 

CLOSED- 
2S6.KRDM 




z^g'/^ 'tzeof/a 



& 




NC 

128/fc4 



15 



i;0.5£L Ifc 



BA 

R/W 
AEC 



CHAREN RSiE 

CZ5CT5(?Sfii|o 

vTt 
fRCRfl 




Di wHa 




74L5Z44 






vZDA S 



2D5 



s£D3 I' 



kZD2 
kZDI 



13 



15 

T7 



RP7 
3.3K 

■^VNA/ O 




T 




CI4 



.{ 




♦ 5V 



74LS2S1A 



14 



*SV 



740(, 




_C37 




MUX 



■H5V 



4-I2V 



R35 

IOOjV 



R45 
I.2K 






MAS 
MA4 

Vic FIX 



ROMH 
ROME 

OWE 

Tcnr 




ROMBAMKHI H 



RQMBANKLO 18 JJJ^g 



R33 ia*f 





M 12 



<«^ 



II 



TUCS 



38 



i^ 



MSB 
M52 
MSI 8721 

PLA 
I?B/25fc 



2SCI8IS 



I 



"7407 

(3 








CTWE CASEnB 



VAI4 



32 CLRBMK 



41 





74F 32 



F R/W 
AUDIO OUT 
D£&-D7 
AB - AI5 



D 




VMA7 

VMAfe 



1VMA5 



VWA4 



MUX 



>VMA,3 



>VMA2 



C 



VMAl 



>VMA« 



> MAOt - MA7 




AEC 



> TA8-TAI5 / 
MAB - MAI I 




>Z80 PHI 



B 




GWE 

ROM^ 



_ LORAM 

vTt 

FROMI 





H 

> RGml 

DWF 



CLRBNK 



i 
I2a/(c 4 

F5DIB 



A 



MICROPROCESSORS, MMU, SID, 

PLA, POWER SUPPLY 
SCHEMATIC 310378 REV- 7A 



Sheet 2 of 4 



t 



3 



1 



74 



QUICK REFERENCE 



TITLE 


PAGE 


2016 


17 


4066 


57 


4416 


19 


556 


57 


74XXX 


58 


8563 


38 


8564 


35 


8701 


30 


BUS ARCHITECTURE 


4 


CLOCK 


30 


LINE DEFINITIONS 

1 


56 


MEMORY ARCHITECTURE 


11 


MODULATOR 


77 


RAM 


17 


ROM 


15 


VIC 




Text 


33 


Pin Configuration 


35 


VIDEO CONTROLLER 




Text 


36 


Pin Configuration 


38 


VIDEO INTERFACE 


33 



8 



3 



1 



AUDIO OUT 

vit 




6ii 



IDACC i 

TAB-TAH 
CLRBNK 



> 




D 



SA0^SA7 



At-AT l ^'"> 






L55 

.U/ 









(f 



± 



a:- 



s; 



7 



i. I 



kA0 



d 



0>W>« 



CAPSLK 




fZ H/U I 

CHAROM 
CQLORftM 




D(J-D1 I 






VAI4 

VAI5 

VMAffl-VMA7 





D(2-D7 [ 



B 



A(2 




F R/W 
RESET 



LP 







ti 



J^ 



I? 



U55 






0£ 



i SlAZ/ 



6Auy 



SA5, 



1^ 



SA4 



11 



(3 



SA^y 



IS 



SAi 



)7 



5AiV 



CI7 



* LV 



74AL^S73 



,l«/ 



VMA 
■^VMAI 




VMA 




10 




II 



bA7 



SAb 



SA5 



,A4 



SAJ 



ML 



iAI 




6A 



■C 



CIS 

.1^ 



'SV 



SA7 



I 



5Afe 



lA^ 



3 



A7 
AU 



^SA^ 



SA2 



SAl 



^SAg B 



TA 1 1 IS 



AEC 



Al« IS 



fl<l 22 



fl& ^ 



o-J 



2f 




+ ^V 



^ 



\d 



C&6 




J5 8008 Dfc -^ 
At "^^ 



ML')74 



n 



Dl 



Dfe 



05 



0^ 



D3 






02 



All 
A 11^ 
AS 

A8 



Ot 



U 



Dl 



Off) 



a® 



il 



II 



14 



n 



10 



D 






CLK 
CLR 



B 




13 



45V 




+ 5V 



r//7 



>5VO 






^isvei 



z 



C//9, .Of^f 





D7 



10 



vss 

DA7 
OA<D 
DAS 
DA4 

DA3 

DA2 
DAI 
OAB 



32 DAfev 
31 DAB. 



30 DA4 
29 DA3 



n 



> 



13 



D4 



.D3 IS 



\k> 



vDI 



I 7 



<D^ Lfi 



2MHZ 4 c^ 



23 



25 



85t3 

D5 

D4 

D3 

D2 

Dl 

D(Z 



33 DA7 



' 



*5V 




DDl 



n 




Z6 DA2 



a? DAI y 



?fe DAB 




DR/M 



21 DP/W 



CCLK 

DI5PEN 
TST 



7 




cs 

R/» 



■Wf. 



LPENz 



B 

I 

VStN 



AS 



44 



4-3 



3 UO 




\<i> 



DRfW 4 



VDDVSSE 
04 A7 

D3 At. 

D2 ,7,A5 
Dl LJ*^ A4 

_44 IC A3 

CAS A2 
^ Al 

V\ A0 






8 0A4 



DA7 



y 



DA fa 



DAS 



11 



DA3> 



DA? 



13 DAI 



14 OAQ 




kC£21 




D.U25,, 



0A7> 



DAfc 



DAS 



DA4 



II DA3 



DA2 



13 DAI 



14 DAa 



+ 5V 



74L5244 




+ 5V 



R4I 
fcao-n. 




I 



8 



II 



Al A2A3A4 
Bl 




DC 



Dt 



la D?) 



w; 



t5V 



74LS25 7A 



N.C. 



VMA7 



VMA& 4 




C2fc 




ZVAI^ 

W 7 




Dil 43 



Dig 44 






lOACC 



rjii »Si4(fJX. 



5D7 47 



K5D(g 
^SDS 



I 



SD4 3 

SD3 ' 



502 



5DI 



5 Off; 



14 



VAl 31 



VAfc 36 



S 
^ 



/f 



orfy?? 



74te\ 



/ - 



TAN 31 




42 



41 



4e 



V MAS 31 
^ VMA4 3fa 




VMA234 



^V^iA" 



33 






DS 
D8 



U2 



C55 

RAS 



DMARQST 
DMA AC K 
EflOPHI 

Kffl 

Kl 

K2 

IMH2 
2MHf 

BA 



D7 

DCd 

DS 

D4 

D3 

D2 

D! 

DO) 

R/W 

A7 

AG 



££. 



L2 2.Z*-H 



■'.f/ 



ir. 



^ f(IOt 



ft 



i3V 




U' 



llf'h 




*5v 



D 



Ji 

— o 



M.C. 
O 



OPEN- KllbC 
CLOSED - PAL 




^ I 



17.7^447 MH< PAL 
CL = \hsA 

C2(Z 

4.C^ - AQ.^c,\ 



1=1 



I I 



L5 
2 



■vr 



2lr 



Z7 



26 



B 



DOT CLOCK 
CAS 






> RAS 



> DIMH7 



< 



> 2B0 t=HI 



2r 




L3 
?.2-H 



SYNC 
LUM 

CHROMA 



n 



■'TBI? 



MAI I 

MAie 
MAS 

MA8 

MAS 
MA4 

MA3 
MA2 
MAI 
MAS 



MUX 
AEC 



IG 



4fB20r 



21 MUX 



IZ AEC 



. CS4 .22./ _ 



RF GUT 







> I MH? 
BA 



,. OPEW : IPA 
■Jll, CLOSED- &PA 



c 



SYNC/ 
LUM 



RF Ml 

MCDL^LATOR 

COMP! 
SYNC4LUM 
OUT 

CHROMA CHROMA 

-3^ 



EMI 39 
270 PF 




+ 5VO — ^ 



CASE 



5 



te 



7 



lOOPF 



mopr 



100 PF 





EMI 40 




EMI 41 



h 




EMI 4 2 



EMI 42 
^ AUDIO OUT 




I 



R25 ie(?K 

5^ 



MC 
-{FET4} 

Mi— 



B 
2 

I 

7 
3 

5 



CN8 

zo 



7 Q 



2 

ex 

00 



a 



> 




.U+CS3 



^ > £X7 AUDIO 



-J 




MUX 

AEC 



RED 



a 



n 




13 



- 11 



15 



I A3 ir3 



IA4 
2A4 

2A2 

2AI 
2A3 



IY4 



2YI 
2Y 



4BV 



C(2Z 



ces * 

IfeV 




C81 
\1ZAT 



Vcc 
l&MHZ 

XTAL Yl 
MODULE 

&ND 




wr^ 



GR£EN[ 



Ife 



BLUE 



14 



4pB44^ i Ei^ll^ 



MI45 




M14fc 



INTEN 



12 








JFB47 



eMT47 



R2(b 



2SC18I5 



2SCISI5 



7406 

_2 



^ 



R3^ 
l2©rL 



740fc 



': 



4^ 






MONOCHROM 



RI& 
82^ 



Q5 
25CI8 




Rn 

33® i\ 



Jf|48] ^*^^^ 



H5fNC 



V5YNC 



CSTR 





+ 5V 



■F e49 . 

iFB5Q^ 
EMI 50 



EMI 49 



± 



3 
4 

5 

7 

a 

9 

/ 



CNI0 



tr 









,+5V Tir.OiitF 




Ffsn 



> o^f «jf r 



lis HIGH £AJD ONLf 



VIDEO, CLOCK, RESET 
SCHEMATIC 310378 REV. 7A 

Sheet 3 of 4 



8 



6 




3 



1 



B 



75 



QUICK REFERENCE 



TITLE 


PAGE 


23128 


16 


4164 


18 


74XXX 


58 


BUS ARCHITECTURE 


4 


LINE DEFINITIONS 


56 


MEMORY ARCHITECTURE 


11 


RAM 


17 


ROM 


15 



8 



7 



6 



5 



i 



4 



3 



2 



1 



TAIZ 
I2B ItA 



C34,, 



D 



OPEN IZSK ROM 
CLOSE -Z5C>KR0M J M 

TAI4 



AA-ArS 



c 




B 



TH»-1MS 




D 



c 




B 



MAC-MAI 

Da- tn 



A 



A 



8 



7 



6 



RAM, ROM 
SCHEMATIC 310378 REV. 7 

Sheet 4 of 4 



76 



5 




4 



3 



2 



1 



RF MODULATOR 



LUMI IN 



COLOR IN O 



AUDIO IN O 



+ B 




O LUMI OUT 



COMP OUT 



O COLOR OUT 



Q1 . Q2: 2SC458 - OR EQUIVALENT 



Q3, Q4: 2SC460 OR EQUIVALENT 



D1, D4: 1SS119 OR EQUIVALENT 



02, 03: 1SS198 OR EQUIVALENT 



COMPONENT PARTS VALUE: R = Q,C = F,L = H 



L9 



024 
150p 



R25 68 



160 




12p 




RF OUT 



GROUND 



11 



FOR REFERENCE ONL Y 



POWER SUPPLY SCHEMATIC 



MITSUMI 



PN-252449-0 1 



T1 



F2 
1.5A 
125V 




9VAC 



+ 5VDC 



G 




78 



FOR REFERENCE ONL Y 



POWER SUPPLY SCHEMATIC 



DEE-VAN 



PN-252449-03 



5A 



1.6A 




9VAC 



O +5VDC 



G 



79 



MAJOR PARTS LIST 



PCB ASSY C128D NTSC 



MANUAL 



USERS 



KEYBOARD ASSY NTSC 
CASE TOP 

CASE BOTTOM 

BEZEL, FRONT NEWT 



KNOB 

DRIVE ASSY 
STAND-OFF 



NEWT 



FOOT, SELF-ADHESIVE 

NAMEPLATE 

POWER SUPPLY ASSY UL, CSA MITSUMI 

POWER SUPPLY ASSY UL, CAS DEE-VAN SUB FOR -01 

RF MODULATOR, PAL 
CARTRIDGE GUIDE 
SHIELD BOX 

SHIELD CAP ASSY 
DISKETTE DEMO 1571 



MANUAL 



SERVICE 



C250477-01 
C354 114-01 
C250735-02 

C252454-01 
C252455-01 
C252457-01 
C252050-01 
C252083-02 
C252461-01 
C950 150-01 
C25 1889-01 
C252449-01 
252449-03 
252404-01 
C3261 16-01 
C326265-01 

C3 10407-01 
C252093-01 
C3 14980-01 



C - Indicates Commodore Stocked Part Number 



SERVICE PARTS REFERENCE DIAGRAM 



ITEM 


PART NUMBER 


DESCRIPTION 


1 

1 


250477-01 


PCB ASSY, C128D NTSC 


1 

2 I 

1 


252449-01 

1 


POWER SUPPLY ASSY UL 
CSA. MITSUMI 


3 


2522083-02 


FLOPPY DISK DRIVE, NEWT 


4 


252455-01 


BOTTOM CASE 


5 


252457-01 


FRONT BEZEL, NEWT 


6 


252050-01 


KNOB 


7 


2522461-01 


STANDOFF- POWER SUPPLY 


8 


9501 50-03 


FOOT, SELF-ADHESIVE 


9 


251889-01 


NAME PLATE 


10 


906800-03 


SCREW, PHILLIPS, PANHEAD, 
M3X8L FOR PCB (14) OTY 


11 


906801-02 


SCREW, PANHEAD WASHER 
FACED, M3X8L FOR FRONT 
BEZEL (3) QTY 


12 


325544-03 


SCREW, PHILLIPS, PANHEAD 
W/FLAT WASHER, M3X8L 
FOR PWR SUPPLY (4) QTY 


13 


325541-03 


SCREW, PHILLIPS, PANHEAD. 
W/EXT. TOOTNED M3X8L 
FDD (3) QTY 


14 


906883-01 


SCREW, SEL-TAPPING, 
PHILLIPS, BIND HEAD M3X8L 
(2) QTY 


NOT SHOWN 




252454-01 


TOP CASE 




350108-01 


SCREW, PANHEAD W/F/W 
M4X8L (5) QTY 




80 



COMPONETS PARTS LIST 

PCB ASSEMBLY ^50477 



U41 

U5 

U21 

U11 

U7 

U10 

U18 

U27 

U19, 103 

U18 

U2, 20 

U23, 25, 38-40 

U1,4 

U28 

U6 

U22 

U32 

U34 

U17 

U55 

U9 

U107 

U104, 106 

U104, 106 Sub. 

U102 

U108 

U108 Sub. 

U108 Sub. 

U109 

U109 Sub. 

Q101 

Q301 

Q101 Sub. 

Q1,2 

DPI, 3 

DP2, 4 

CR301 

Ml 

CT1 

SW1, 2 

CN5 



IC 64K X 4 DRAM 

IC SID 8580 

IC VIC 8564 NTSC 

IC PAL 8721 

IC MMU 8722 

IC Z80 B 6MHZ 

IC CHAR ROM 

IC NE556 

IC 2016 20LB 2K X 8 

IC 8006 C128/C64 CHAR ROM 

IC 4066 

IC 64K X 4 DRAM 150NS 

IC 6526 

IC 8701 

IC 8502 MPU 

IC 8568 80 COL CRT CNTRL 

CI 28 ROM 2/3 (UK) 

CI 28 ROM 1/4 

IC 74ALS373 

74F245 

74F32 

FDC 5710 

VIA 6522A 2 MHZ 

IC65SC22A 1MHZ 

EP-ROM 27256 300NS 

FDD R/W AMP SONY CX20185 

FDD R/W AMP MOTOROLA MC28719 

FDD R/W AMP SANYO LA8200 

UPA2003C NEC 

IC IR2C19 SHARP 

TRANS 2SA683 

TRANS 2SD880 

TRANS MPSU51 

TRANS 2SC1815 

DIODE ARRAY 7 PIN 

DIODE ARRAY 7 PIN 

DIODE ZENER RD 6.8 EB 

RF MODULATOR NTSC 

TRIMMER CAP 6.5- 40P 

RESET BUTTON 

CONNECTOR MALE 25 PIN 



390083-02 

C31 801 3-01 

C3 15009-01 

C31 501 2-01 

C3 10389-01 

9061 50-02 

C3 15079-01 

901523-03 

251637-05 

C390059-0 1 

901502-01 

390083-02 

C906 108-01 

C25 1527-07 

C3 15020-01 

C3 15092-01 

318023-02 

C3 18022-02 

390058-01 

252208-01 

390077-01 

C252371-01 

C90 1 437-02 

310653-01 

C252372-01 

C252308-0 1 

252308-02 

252308-03 

C251871-01 

251871-02 

252400-0 1 

902694-0 1 

310657-01 

902693-01 

C252333-01 

C252333-02 

900927-0 1 

C252405-0 1 

C25 1029-02 

C25 1260-01 

C359002-02 



C-lndicates CBM Stocked Part Number 



BOARD LAYOUT 



PCB ASSEMBLY #250477-01 






12 



CN8 






C78 



() 






s 



3 



C4 



IS 



Z C64U 



C76 



C67 



6 

I 



9 
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CN2 



c 



RPt 



llllll 



r 8 S u O oS 



gee 



?o? ?: 



Op. 



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L 



C22 



en 






J 



C23 
C24 



C25 



() 



C57 



S 




U 



tn 



J 



J)i^ 



jto 



jii 



C28 



C70 



N 



() 



Y2" ♦ 



N 



CTI 



01 




C28 



8 



R39 



MU 



3 



,1 






p^s 



r> I— 



C2I 



Ml 



e e 



a 



o 



CM 






J 
17 



JI6 



1 2 3 

4 5 

6 « 



^nCNS 



I 3 5 

2 4 



CN6 







L3 






o 

40 



ID 



4n 
u 



s 



s 



ceo 



CI6 



CSS 



» 



h 



R2 






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SCHEMATIC #252451 



Sheet 1 of 5 



I 



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tsy 



4T PF 



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82 



SCHEMATIC #252451 



Sheet 2 of 5 



CM AUDIO 



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83 



SCHEMATIC #252451 



Sheet 3 of 5 



AUDIO OUT 

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84 



SCHEMATIC #252451 



Sheet 4 of 5 



Ii8 / 64 





U1 dJffF 



7 A 14 




AfJ 




74 1^09 



/ 



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Z 



A t 




A 



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J 


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4 


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6 


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7 


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9 



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1 



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7Ai-^TA/S 
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85 



SCHEMATIC #252451 



Sheet 5 of 5 



Hii/4 



> GNDtltr}[[] 



itrn 



CND ( iO€/C i 



*•'*' .0/i/F .OUF mr .9IUF 

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5 



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ij TH/^ sc/fSM/trfc MFsrs //m^r/tOMCS ds02 asfr o/t/v^ , 



86